AI/ML systems have been deployed in both SoC design/architecture as well as in semiconductor manufacturing over the years. These systems have been independent of each other with process design kits (PDK) being the interface between design and manufacturing. Recent advances in packaging technology and the adoption of chiplet architecture has opened exciting avenues for merged AI/ML systems that bring SoC architecture and manufacturing together. This work explores this opportunity of enabling an AI/ML system that brings manufacturing and design information together for chiplet architecture exploration

Silicon-based CMOS technology can be scaled well into the nanometer regime. High-performance, planar, ultrathin-body devices fabricated on silicon-on-insulator substrates have been demonstrated down to 15-nm gate lengths. We have also introduced the FinFET, a double-gate device structure that is relatively simple to fabricate and can be scaled to gate lengths below 10 nm. In this paper, some of the key elements of these technologies are described, including sublithographic patterning, the effects of crystal orientation and roughness on carrier mobility, gate work function engineering, circuit performance, and sensitivity to process-induced variations.