Demo Data from SIGIR 2026 / reviewers in the wild / expert
Adiwena Putra
dblp:304/9157
· DBLP profile ↗
4ranked-venue papers
1as first author
4since 2021 · last 2025
0000-0001-6963-566XORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 1 first-author · 4 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
4 papers |
Hardware accelerators and domain-specific architectures · 97% GPUs and heterogeneous computing · 3% | |
| Network and information security
3 papers |
Cryptographic primitives and cryptanalysis · 100% |
Topics — the 11 heaviest of 11, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Cryptographic primitives and cryptanalysis › homomorphic encryption
fully homomorphic encryption |
1.6 | 2 | 2025 | ABC-FHE: A Resource-Efficient Accelerator Enabling Bootstrappable Parameters for Client-Side Fully Homomorphic Encryption · DAC 2025 Morphling: A Throughput-Maximized TFHE-based Accelerator using Transform-domain Reuse · HPCA 2024 |
Hardware accelerators and domain-specific architectures
cryptographic accelerator |
1.5 | 2 | 2025 | ABC-FHE: A Resource-Efficient Accelerator Enabling Bootstrappable Parameters for Client-Side Fully Homomorphic Encryption · DAC 2025 Strix: An End-to-End Streaming Architecture with Two-Level Ciphertext Batching for Fully Homomorphic Encryption with Programmable Bootstrapping · MICRO 2023 |
Hardware accelerators and domain-specific architectures › cryptographic accelerator
fully homomorphic encryption accelerator |
1.5 | 2 | 2025 | ABC-FHE: A Resource-Efficient Accelerator Enabling Bootstrappable Parameters for Client-Side Fully Homomorphic Encryption · DAC 2025 Strix: An End-to-End Streaming Architecture with Two-Level Ciphertext Batching for Fully Homomorphic Encryption with Programmable Bootstrapping · MICRO 2023 |
Cryptographic primitives and cryptanalysis › homomorphic encryption › fully homomorphic encryption
TFHE |
1.4 | 2 | 2024 | Morphling: A Throughput-Maximized TFHE-based Accelerator using Transform-domain Reuse · HPCA 2024 Strix: An End-to-End Streaming Architecture with Two-Level Ciphertext Batching for Fully Homomorphic Encryption with Programmable Bootstrapping · MICRO 2023 |
Hardware accelerators and domain-specific architectures › machine learning accelerator › neural network accelerator
diffusion model accelerator |
0.9 | 1 | 2025 | EXION: Exploiting Inter-and Intra-Iteration Output Sparsity for Diffusion Models · HPCA 2025 |
Hardware accelerators and domain-specific architectures
machine learning accelerator |
0.9 | 1 | 2025 | EXION: Exploiting Inter-and Intra-Iteration Output Sparsity for Diffusion Models · HPCA 2025 |
Hardware accelerators and domain-specific architectures › cryptographic accelerator
homomorphic encryption accelerator |
0.8 | 1 | 2024 | Morphling: A Throughput-Maximized TFHE-based Accelerator using Transform-domain Reuse · HPCA 2024 |
Cryptographic primitives and cryptanalysis
homomorphic encryption |
0.7 | 1 | 2023 | Strix: An End-to-End Streaming Architecture with Two-Level Ciphertext Batching for Fully Homomorphic Encryption with Programmable Bootstrapping · MICRO 2023 |
Machine learning › Efficient and distributed learning
inference acceleration |
0.3 | 1 | 2025 | EXION: Exploiting Inter-and Intra-Iteration Output Sparsity for Diffusion Models · HPCA 2025 |
Hardware accelerators and domain-specific architectures
systolic array |
0.2 | 1 | 2024 | Morphling: A Throughput-Maximized TFHE-based Accelerator using Transform-domain Reuse · HPCA 2024 |
GPUs and heterogeneous computing
GPU computing |
0.2 | 1 | 2023 | Strix: An End-to-End Streaming Architecture with Two-Level Ciphertext Batching for Fully Homomorphic Encryption with Programmable Bootstrapping · MICRO 2023 |
Methods — techniques the papers use, named apart from their topics
reconfigurable fourier engine · 1.7on-the-fly twiddle factor generation · 1.7NTT/FFT · 1.7transform-domain reuse · 1.5FFT · 1.52d systolic array · 1.5programmable bootstrapping · 1.3ciphertext batching · 1.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | ABC-FHE: A Resource-Efficient Accelerator Enabling Bootstrappable Parameters for Client-Side Fully Homomorphic EncryptionabstractAs the demand for privacy-preserving computation continues to grow, fully homomorphic encryption (FHE)—which enables continuous computation on encrypted data—has become a critical solution. However, its adoption is hindered by significant computational overhead, requiring 10000-fold more computation compared to plaintext processing. Recent advancements in FHE accelerators have successfully improved server-side performance, but client-side computations remain a bottleneck, particularly under bootstrappable parameter configurations, which involve combinations of encoding, encrypt, decoding, and decrypt for large-sized parameters. To address this challenge, we propose ABC-FHE, an area- and power-efficient FHE accelerator that supports bootstrappable parameters on the client side. ABCFHE employs a streaming architecture to maximize performance density, minimize area usage, and reduce off-chip memory access. Key innovations include a reconfigurable Fourier engine capable of switching between NTT and FFT modes. Additionally, an onchip pseudo-random number generator and a unified on-the-fly twiddle factor generator significantly reduce memory demands, while optimized task scheduling enhances the CKKS clientside processing, achieving reduced latency. Overall, ABC-FHE occupies a die area of 28.638 mm2 and consumes 5.654 W of power in 28 nm technology. It delivers significant performance improvements, achieving a 1112× speed-up in encoding and encryption execution time compared to a CPU, and 214× over the state-of-the-art client-side accelerator. For decoding and decryption, it achieves a 963× speed-up over the CPU and 82× over the state-of-the-art accelerator. Sungwoong Yune, Adiwena Putra, Hyunjun Cho, Cuong Duong Manh, Joo-Young Kim 0001 |
DAC | 3 |
| 2025 | EXION: Exploiting Inter-and Intra-Iteration Output Sparsity for Diffusion Models
Jaehoon Heo, Adiwena Putra, Jieon Yoon, Sungwoong Yune, Hangyeol Lee, Ji-Hoon Kim 0004, Joo-Young Kim 0001 |
HPCA | 2 |
| 2024 | Morphling: A Throughput-Maximized TFHE-based Accelerator using Transform-domain ReuseabstractFully Homomorphic Encryption (FHE) has become an increasingly important aspect in modern computing, particularly in preserving privacy in cloud computing by enabling computation directly on encrypted data. Despite its potential, FHE generally poses major computational challenges, including huge computational and memory requirements. The bootstrapping operation, which is essential particularly in Torus-Fhe(tfhe) scheme, involves intensive computations characterized by an enormous number of polynomial multiplications. For instance, performing a single bootstrapping at the 128-bit security level requires more than 10,000 polynomial multiplications. Our in-depth analysis reveals that domain-transform operations, i.e., Fast Fourier Transform (FFT), contribute up to 88% of these operations, which is the bottleneck of the TFHE system. To address these challenges, we propose Morphling, an accelerator architecture that combines the 2D systolic array and strategic use of transform-domain reuse in order to reduce the overhead of domain-transform in TFHE. This novel approach effectively reduces the number of required domain-transform operations by up to 83.3 %, allowing more computational cores in a given die area. In addition, we optimize its micro architecture design for end-to-end TFHE operation, such as merge-split pipelined-FFT for efficient domain-transform operation, double-pointer method for high-throughput polynomial rotation, and specialized buffer design. Furthermore, we introduce custom instructions for tiling, batching, and scheduling of multiple ciphertext operations. This facilitates software-hardware co-optimization, effectively mapping high-level applications such as XG-Boost classifier, Neural-Network, and VGG-9. As a result, Morphling, with four 2D systolic arrays and four vector units with domain-transform reuse, takes 74.79 mm2die area and 53.00 W power consumption in 28nm process. It achieves a throughput of up to 147,615 bootstrappings per second, demonstrating improvements of 3440x over the CPU, 143x over the GPU, and 14.7x over the state-of-the-art TFHE accelerator. It can run various deep learning models with sub-second latency. Prasetiyo, Adiwena Putra, Joo-Young Kim 0001 |
HPCA | 2 |
| 2023 | Strix: An End-to-End Streaming Architecture with Two-Level Ciphertext Batching for Fully Homomorphic Encryption with Programmable BootstrappingabstractHomomorphic encryption (HE) is a type of cryptography that allows computations to be performed on encrypted data. The technique relies on learning with errors problem, where data is hidden under noise for security. To avoid excessive noise, bootstrapping is used to reset the noise level in the ciphertext, but it requires a large key and is computationally expensive. The fully homomorphic encryption over the torus (TFHE) scheme offers a faster and programmable bootstrapping (PBS) algorithm, which is crucial for many privacy-focused applications. Nonetheless, the current TFHE scheme does not support ciphertext packing, resulting in low-throughput performance. To the best of our knowledge, this is the first work that thoroughly analyzes TFHE bootstrapping, identifies the TFHE acceleration bottleneck in GPUs, and proposes a hardware TFHE accelerator to solve the bottleneck. Adiwena Putra, Prasetiyo, Yi Chen 0035, John Kim 0001, Joo-Young Kim 0001 |
MICRO | 1 |