Demo Data from SIGIR 2026 / reviewers in the wild / expert
Chandrahas Tirumalasetty
dblp:309/6461
· DBLP profile ↗
1ranked-venue papers
1as first author
1since 2021 · last 2022
0000-0001-8333-7896ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 80% Hardware accelerators and domain-specific architectures · 20% | |
| Software engineering, system software, and programming languages
1 paper |
Operating systems · 100% |
Topics — the 6 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems › memory management › virtual memory
address translation |
0.6 | 1 | 2022 | Reducing Minor Page Fault Overheads through Enhanced Page Walker · ACM Trans. Archit. Code Optim. 2022 |
Memory systems › memory management › virtual memory
page fault handling |
0.6 | 1 | 2022 | Reducing Minor Page Fault Overheads through Enhanced Page Walker · ACM Trans. Archit. Code Optim. 2022 |
Memory systems › memory management › virtual memory › address translation
TLB |
0.6 | 1 | 2022 | Reducing Minor Page Fault Overheads through Enhanced Page Walker · ACM Trans. Archit. Code Optim. 2022 |
Memory systems › memory management
virtual memory |
0.6 | 1 | 2022 | Reducing Minor Page Fault Overheads through Enhanced Page Walker · ACM Trans. Archit. Code Optim. 2022 |
Operating systems › resource management
memory management |
0.2 | 1 | 2022 | Reducing Minor Page Fault Overheads through Enhanced Page Walker · ACM Trans. Archit. Code Optim. 2022 |
Operating systems › resource management › memory management
page allocation |
0.2 | 1 | 2022 | Reducing Minor Page Fault Overheads through Enhanced Page Walker · ACM Trans. Archit. Code Optim. 2022 |
Methods — techniques the papers use, named apart from their topics
hardware-software co-design · 1.1gem5 simulation · 1.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2022 | Reducing Minor Page Fault Overheads through Enhanced Page WalkerabstractApplication virtual memory footprints are growing rapidly in all systems from servers down to smartphones. To address this growing demand, system integrators are incorporating ever larger amounts of main memory, warranting rethinking of memory management. In current systems, applications produce page fault exceptions whenever they access virtual memory regions that are not backed by a physical page. As application memory footprints grow, they induce more and more minor page faults. Handling of each minor page fault can take a few thousands of CPU cycles and blocks the application till the OS kernel finds a free physical frame. These page faults can be detrimental to the performance when their frequency of occurrence is high and spread across application runtime. Specifically, lazy allocation-induced minor page faults are increasingly impacting application performance. Our evaluation of several workloads indicates an overhead due to minor page faults as high as 29% of execution time. In this article, we propose to mitigate this problem through a hardware, software co-design approach. Specifically, we first propose to parallelize portions of the kernel page allocation to run ahead of fault time in a separate thread. Then we propose the Minor Fault Offload Engine (MFOE), a per-core hardware accelerator for minor fault handling. MFOE is equipped with a pre-allocated page frame table that it uses to service a page fault. On a page fault, MFOE quickly picks a pre-allocated page frame from this table, makes an entry for it in the TLB, and updates the page table entry to satisfy the page fault. The pre-allocation frame tables are periodically refreshed by a background kernel thread, which also updates the data structures in the kernel to account for the handled page faults. We evaluate this system in the gem5 architectural simulator with a modified Linux kernel running on top of simulated hardware containing the MFOE accelerator. Our results show that MFOE improves the average critical path fault handling latency by 33× and tail critical path latency by 51×. Among the evaluated applications, we observed an improvement of runtime by an average of 6.6%. Chandrahas Tirumalasetty, Chih-Chieh Chou, A. L. Narasimha Reddy, Paul Gratz, Ayman Abouelwafa |
ACM Trans. Archit. Code Optim. | 1 |