In intermittent computing enabling continuous information processing under unstable energy supply, it is important to minimize the energy consumption required to maintain intermediate information during frequent power supply interruptions. In this paper, we propose a new configuration of a magnetic-tunnel-junction (MTJ)-based nonvolatile register that can save intermediate information during intermittent operation in a short time with low energy consumption. The proposed nonvolatile register adopts a differential information storing scheme that expresses one-bit data by assigning ‘1’ when the states of two adjacent MTJ devices are the same and ‘0’ when they are different. This reduces the circuit area and energy consumption by reducing the number of MTJ devices in a register, as well as achieving quick backup and restoration by accessing MTJ devices in parallel. The evaluation using a 55 nm CMOS/MTJ-hybrid process technology shows that the proposed nonvolatile register can reduce the circuit area and energy consumption by 34% and 49%, respectively, compared to those of a conventional one.

It is an attractive feature to make the capacity of power storage as small as possible in battery-free devices, while it may cause task failure frequently because of its unsatisfactory amount of power storage. This paper describes the design of a power control circuit using a threshold adjustment unit (TAU), that can adjust the energy harvested by a battery-less device for different tasks. The scheme sets a properly sized capacitor as power storage, which can adjust its power capacity prepared for tasks with different power consumptions by changing the charging and discharge threshold, thus avoiding task failure caused by insufficient power supply. Meanwhile, the high-speed and low-power design of this scheme can reduce the overhead caused by judging the charging/discharging voltage and the threshold voltage. By applying this unit to a battery-free configuration that assumes RF power feeding, charge and discharge path control at various thresholds in intermittent computing can be completed automatically and with low overhead. With the simulation of HSPICE based on 45nm CMOS, the average power consumption and response delay of the proposed trigger circuit with double-rail discrete-time comparator are only 45.9μW and 39.0μs, respectively.

Power gating (PG) is an important technique of energy-efficient LSIs to realize additional applications for Internet-of-Things devices in the future, but it also has issues including circuit performance degradation and increased area overhead. In this paper, we designed a new PG switch array with its control unit based on an optimum switch-timing control scheme to obtain a high-performance/low-area implementation. According to the simulation results based on 45nm CMOS under HSPICE, the maximum inrush current is reduced by up to 95.6% and the minimum wake-up-time is only 0.22ns.

Magnetic-Tunnel Junction (MTJ)-based non-volatile logic circuits have some possibility to solve the power-dissipation problem seriously focusing on the present CMOS-only-based VLSI processors. Three terminal MTJ devices are the promising candidate as nonvolatile storage device to realize such a nonvolatile logic circuit. However, its writing energy is still serious in comparison with conventional CMOS-only-based logic circuits. In this paper, a new MTJ-based nonvolatile logic circuit with self-terminated mechanism is proposed and its energy efficiency is evaluated in comparison with the corresponding previous work. In addition, some recent research topics related to MTJ-based nonvolatile logic-circuit design and its application, such as a computer-aided-design (CAD) tool considering a stochastic MTJ-switching behavior and the application to a resilient “die-hard” VLSI processor against sudden power-supply outage, are also demonstrated.

A new VLSI CAD environment considering stochastic behavior of MTJ devices is proposed for the evaluation of not only the performance but also the reliability of MTJ/MOS-hybrid logic LSI. The proposed simulator allows users to support the design of MTJ/MOS-hybrid LSI by RTL/gate-level hardware description, whose simulation considering stochastic switching behavior of MTJ device can be done by analog-mixed-signal simulation with de-facto standard EDA tools. Through the design of a nonvolatile logic LSI based on a general purpose 32-bit microprocessor, the impact of the proposed design flow is demonstrated.

Nonvolatile spintronic devices have potential advantages, such as fast read/write and high endurance together with back-end-of-the-line compatibility, which offers the possibility of constructing not only stand-alone RAMs and embedded RAMs that can be used in conventional VLSI circuits and systems but also standby-power-free high-performance nonvolatile CMOS logic employing logic-in-memory architecture. The advantages of employing spintronic devices, especially magnetic tunnel junction (MTJ) devices with CMOS circuits, are discussed, and the current status of the MTJ-based VLSI computing paradigm is presented along with its prospects and remaining challenges.

A cell-based design flow for MTJ/MOS-hybrid logic circuits is presented towards the realization of practical-scale logic LSI based on nonvolatile logic-in-memory architecture. Newly-developed supplementary design tools including a precise MTJ device model enable to design MTJ/MOS-hybrid logic's intellectual properties (IPs) accurately. By the use of the IPs, various pattern layouts of the MOS and MTJ/MOS-hybrid logic-circuit cells can be automatically synthesized. The effectiveness of the proposed design flow is demonstrated through typical arithmetic-circuit design examples with a nonvolatile storage capability.

A perpendicular magnetic-tunnel-junction (MTJ)-based 2T-2R ternary content-addressable memory (TCAM) cell is proposed for a high-density nonvolatile word-parallel/bit-serial TCAM. The use of MOS/MTJ-hybrid logic makes it possible to implement a compact nonvolatile TCAM cell with 2.5 μm2of a cell size in a 0.14-μm CMOS and a 100-nm perpendicular-MTJ technologies. By reversed-current reading through the perpendicular MTJ device, tolerability of read disturb is greatly enhanced. Moreover, fine-grained power gating based on bit-level equality-search scheme achieves ultra-low activity rate of 4.1% in a fabricated 72-bit × 128-word nonvolatile TCAM, which results in ultra-low active power and standby power.

A current-mode logic-circuit style using MTJ devices as threshold voltage (Vth) variation compensating elements is proposed for realizing a process-variation-aware VLSI processor with maintaining a higher performance capability. The faulty logic-operation behavior due to Vthvariation of each MOS transistor can be neglected by adjusting resistance values of MTJ devices that are connected to the source electrode of MOS transistors in series. By using HSPICE simulation under a 90nm CMOS technology, it is demonstrated that basic current-mode logic gates using the proposed method are robust against the Vthvariation.

This paper presents a generic objected-oriented framework of evolutionary graph generation (EGG) for automated circuit synthesis. The EGG system can be systematically implemented for different design problems by inheriting the framework class templates. The potential capability of EGG framework is demonstrated through experimental synthesis of both digital and analogue circuits. Design examples discussed in this paper are: (i) bit-serial multipliers using bit-level arithmetic components; and (ii) current mirrors using transistor-level components.