We present the status and direction of silicon semiconductor technologies targeted for applications such as wireless, networking, instrumentation, and storage markets. Various technological aspects for multiple branches of RF foundry technologies that are based on the standard foundry compatible CMOS node are discussed - SiGe BiCMOS HP ("high performance") tailored to high-frequency applications, SiGe BiCMOS WL ("cost performance") tailored to wireless/storage applications, and RF-CMOS optimized for low-cost consumer applications. Future opportunities and challenges for advancement in RF technologies are described in light of CMOS and SiGe heterojunction bipolar transistor scaling. In addition, we discuss the maturity of SiGe BiCMOS by looking at the levels of integration and manufacturability.

A 1.5 GHz-2.0 GHz low noise amplifier (LNA) is designed in IBM 0.18 um BiCMOS technology using IBM design kits in cadence design flow. The fabricated LNA chip is packaged and tested. The measured results (gain, noise figure, and IIP3) correlate with the simulation very well. The results demonstrate that IBM SiGe technology, modeling, design kits and the cadence design flow are solid and accurate for RFIC design.

This paper expands the on-chip interconnect-aware methodology for high-speed analog and mixed signal design, presented in [4], into a wider class of designs, including dense layout CMOS design. The proposed solution employs a set of parameterized on-chip transmission line (T line) devices for the critical interconnects, which is expanded to include coplanar structures while considering the silicon substrate effect. The generalized methodology contains treatment of the crossing line effects at the various design stages, including two way interaction between the post layout extraction tool and the T-line devices. The T-line device models are passive by construction, easily migratable among design environments, and allow for both time and frequency domain simulations. These models are verified by S-parameter measurements up to 110GHz, as well as by EM solver results. It is experimentally shown that the effect of properly designed discontinuities is negligible in most practical cases. The basic on-chip T-line methodology is being used extensively for numerous high-speed designs.

CMOS dominates digital microelectronics. However, wireless applications require RF circuits at 1-5GHz, and exotic higher frequency applications are on the horizon. Silicon-Germanium (SiGe) is a growing choice for these designs. But is it "the" answer? Some argue that scaled CMOS will handle all tomorrow's RF ICs. Others argue that one-chip SoC solutions will never be the winning strategy for these highly heterogeneous designs, and place their bets on system-in-package (SiP) technologies. Is there a right answer here? Is CMOS the "only" way, or just "another" way?