In this paper, we present a systematic approach to design hardware circuits for bit-dimension permutations. The proposed approach is based on decomposing any bit-dimension permutation into elementary bit-exchanges. Such decomposition is proven to achieve the theoretical minimum number of delays required for the permutation. This offers optimum solutions for multiple well-known problems in the literature that make use of bit-dimension permutations. This includes the design of permutation circuits for the fast Fourier transform, bit reversal, matrix transposition, stride permutations, and Viterbi decoders.

Particle filters are a widely used tool to perform Bayesian filtering under nonlinear dynamic and measurement models or non-Gaussian distributions. However, the performance of particle filters plummets when dealing with high-dimensional state spaces. In this paper, we propose a method that makes use of multiple particle filtering to circumvent this difficulty. Multiple particle filters partition the state space and run an individual particle filter for every component. Each particle filter shares information with the rest of the filters to account for the influence of the complete state in the observations collected by sensors. The method considered in this paper uses auxiliary filtering within the MPF framework, outperforming previous algorithms in the literature. The performance of the considered algorithm is tested in a multiple target tracking scenario, with fixed and known number of targets, using a sensor network with a nonlinear measurement model.

A real-time image processing algorithm, using a GPU with NVIDIA's CUDA technology, for a 3-D through-clothes detection radar in the THz band has been developed. Traditional CPU-based architectures lack the computing power and parallelization needed to meet the image refresh rates imposed by the radar's scanning. This solution presents a low-cost and flexible alternative that allows image refresh at a rate of more than 8 fps for images composed of 6,000 pixels, corresponding to a scanned area of 50x90 cm2. The performance of this code has been profiled, with comparison against a previous CPU-executed version, and some optimizations that would enable even faster refresh have been analyzed.

This brief presents a novel 4096-point radix-4 memory-based fast Fourier transform (FFT). The proposed architecture follows a conflict-free strategy that only requires a total memory of size N and a few additional multiplexers. The control is also simple, as it is generated directly from the bits of a counter. Apart from the low complexity, the FFT has been implemented on a Virtex-5 field programmable gate array (FPGA) using DSP slices. The goal has been to reduce the use of distributed logic, which is scarce in the target FPGA. With this purpose, most of the hardware has been implemented in DSP48E. As a result, the proposed FPGA is efficient in terms of hardware resources, as is shown by the experimental results.

Radiometers are commonly used in order to assess the atmospheric propagation channel under low-attenuation and scatter-free conditions, with an increasing tendency toward using millimeter frequencies. In this letter, the interest is concentrated on the analysis of atmospheric attenuation measurements simultaneously obtained, under clear sky and the presence of clouds, by two independent and colocated ground-based radiometers at 19.7 and 99 GHz, in April of 2012 in Madrid, Spain. The experimental results obtained are in agreement with the estimations based on vertical meteorological profiles, and it is relevant to mention the high sensitivity to cloud liquid water provided by the measurements at 99 GHz. In general, the perspective of this work points toward the validity of using millimeter radiometry in propagation applications.

The appearance of radix-22was a milestone in the design of pipelined FFT hardware architectures. Later, radix-22was extended to radix-2k. However, radix-2kwas only proposed for single-path delay feedback (SDF) architectures, but not for feedforward ones, also called multi-path delay commutator (MDC). This paper presents the radix-2kfeedforward (MDC) FFT architectures. In feedforward architectures radix-2kcan be used for any number of parallel samples which is a power of two. Furthermore, both decimation in frequency (DIF) and decimation in time (DIT) decompositions can be used. In addition to this, the designs can achieve very high throughputs, which makes them suitable for the most demanding applications. Indeed, the proposed radix-2kfeedforward architectures require fewer hardware resources than parallel feedback ones, also called multi-path delay feedback (MDF), when several samples in parallel must be processed. As a result, the proposed radix-2kfeedforward architectures not only offer an attractive solution for current applications, but also open up a new research line on feedforward structures.

A new memoryless CORDIC algorithm for the FFT computation is proposed in this paper. This approach calculates the direction of the micro-rotations from the control counter of the FFT, so the area of the rotator hardly depends on the number of rotations, which is particularly suitable for the computation of FFTs of a high number of points. Moreover, the new CORDIC presents other advantages such as the simplification of the basic CORDIC processor used to calculate the micro-rotations, or an easy way to compensate the intrinsic gain of the CORDIC algorithm. Additionally, the VLSI implementation of the algorithm is a pipeline architecture with high performance in terms of speed, throughput and latency.

An algorithm to detect and estimate a linear mixture of signals corrupted by white Gaussian noise is presented. The number of signals is assumed to be unknown. The algorithm is based on a type of information theoretic criterion, capable of adjusting the probability of false alarm, and uses atomic decomposition refined by the expectation maximization method to efficiently compute the maximum likelihood estimate of the signal parameters. Signals are modeled as chirplets. The algorithm consistency and efficiency are shown by simulation.

Two detectors based on the GLRT (generalized maximum likelihood ratio test) are presented to detect a chirplet in coloured Gaussian noise for known and unknown covariance structures, respectively. They are applied to detect multiple chirplets by atomic decomposition, which is modified to account for the operating conditions of both detectors. Both detectors are CFAR with respect to the noise power. The second one is CFAR with respect to the covariance structure as well.

A post-processing detector for Atomic Decomposition in order to evaluate the quality of the extracted signal components is presented. It improves the signal representation and can work in a noisy environment. Its advantages over High Resolution Pursuit are investigated along with its application to the combination of two types of dictionaries to achieve high detection performance and high resolution.

This paper describes how optimization techniques can be applied to efficiently solve the constrained co-design problem. This is performed by the formulation of different cost functions which will drive the hardware-software partitioning process. The use of complex cost functions allows us to capture more aspects of the design. Besides, the appropriate formulation of this kind of functions has a great impact on the results that can be obtained regarding both quality and algorithm convergence rate. A strong point of the proposed formulation is its generality. Therefore, it does not depend on the problem and can be easily extended for considering new design constraints.