The verification complexity of safety-critical systems on chip increased manifold after the introduction of ISO 26262, the safety standard for automotive applications. As a result, checkpoint-restore techniques have been implemented to speed-up fault-injection simulations of register-transfer level and gate-level models. However, these techniques are not suitable for safety verification, since they have high hard-disk space requirements, long generation time, and are mainly generated manually. To address these limitations, in this paper, we present a compiled-code-based snapshotting mechanism, which automatically generates an arbitrary amount of checkpoints post-simulation from a model's simulation traces. Our approach uses three to four orders of magnitude less hard-disk space than commercial tools and generates checkpoints 5x to 12x faster. Finally, fault-injection simulations with our approach run 6.75x to 27x faster than with commercial tools.

Safety-critical systems-on-chip currently undergo extensive fault-effect analyses. To meet the safety requirements of ISO 26262, most frequently fault-injection campaigns are per- formed. Due to the exponentially growing fault-verification space, faster simulation possibilities than enabled by register transfer (RT) and gate-level (GL) models are under investigation. Fault injection on virtual prototypes (VPs) is one measure to speed up simulation. However, VPs require the injection of complex abstract faults to observe the same effects of, for example, single- bit fault injection into GL models. As a consequence, VPs often suffer from injection of incorrect faults (i.e., faults whose effects cannot be reproduced on the RT or gate levels). Therefore, we developed an efficient approach to verify or falsify failures detected with VP fault simulation. As a result, incorrect faults are discovered early in the development phase helping to improve the design of accurate safety mechanisms. Moreover, the exclusion of incorrect faults from fault-effect analyses further improves the accuracy and efficiency of fault-injection campaigns. The benefit of the presented method has been validated using a medium-size controller design.

The need for safer and more robust hardware systems increased considerably in the automotive industry after the introduction of the safety standard ISO 26262. As a result, fault injection became a major verification milestone for safety-critical applications. However, safety-verification methods for gate level (GL) and RTL models suffer from long simulation time and large fault-injection campaigns due to the high complexity of large-scale SoCs. Virtual prototypes (VP) were employed to address the shortcomings of GL and RTL simulation, however fault injection into VPs usually leads to the observation of different failures than into GL and RTL models. In this paper, we present an approach which ensures 100% correlation of faults injected across VPs and GL models. Using a compiled-code approach, we transform GL net-lists into C++ code, which we then integrate into SystemC/TLM-based VPs. Thus, the new VPs have the same accuracy as the GL net-lists and are executed at near VP speed. Furthermore, since the new models share all fault-injection properties with the original GL net-lists, only realistic failures can be observed after fault injection.

Certifying an electrical/electronic system as functionally safe requires a range of analysis and assessment procedures, which must be performed during the different design and manufacturing phases. In the automotive context, the ISO 26262 standard prescribes a set of methods, including FMEDA (Failure Modes, Effects, and Diagnostic Analysis), to evaluate the safety integrity level of the product. FMEDA is a well-established technique in the industry, however, it still demands cumbersome and error-prone manual tasks.

Intelligent automotive electronics significantly improved driving safety in the last decades. With the increasing complexity of automotive systems, dependability of the electronic components themselves and of their interaction must be assured to avoid any risk to driving safety due to unexpected failures caused by internal or external faults.

In this paper, the influence of antenna diversity techniques adapted to the IEEE 802.15.4 radio technology are evaluated and the corresponding process gains are empirically examined. With the assumption of a WSSUS model and Rayleigh-distributed signal amplitudes, the minimum optimal antenna spacing relating to a 2D-propagation is calculated. A diversity module with three antennas, based on Freescale MC13193 transceivers, was developed by using the calculated antenna spacing. Different algorithms for signal combining were examined and evaluated with this module. The process gain of the particular algorithms was quantified by the corresponding error rate and by examination of the RSSI values. Additionally, the effects of the combining algorithms on the "digital" channel's memory were examined. For this purpose the parameters complementary error distance distribution 𝐹𝒶c(𝒶), block error density function 𝑃(𝑚,𝑛) and error correlation function 𝑅𝑒𝑒(𝑣) were used.