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Jer-Ming Hsu

dblp:31/5094 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2003
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design › floorplanning
b*-tree representation
0.012003
Multilevel floorplanning/placement for large-scale modules using B*-trees · DAC 2003
Electronic design automation › physical design
floorplanning
0.012003
Multilevel floorplanning/placement for large-scale modules using B*-trees · DAC 2003
Electronic design automation
physical design
0.012003
Multilevel floorplanning/placement for large-scale modules using B*-trees · DAC 2003

Methods — techniques the papers use, named apart from their topics

simulated annealing · 0.0clustering · 0.0
YearPublicationVenuePosition
2003 Multilevel floorplanning/placement for large-scale modules using B*-trees
abstract
We present in this paper a multilevel floorplanning/placement framework based on the B*-tree representation, called MB*-tree, to handle the floorplanning and packing for large-scale building modules. The MB*-tree adopts a two-stage technique, clustering followed by declustering. The clustering stage iteratively groups a set of modules based on a cost metric guided by area utilization and module connectivity, and at the same time establishes the geometric relations for the newly clustered modules by constructing a corresponding B*-tree for them. The declustering stage iteratively ungroups a set of the previously clustered modules (i.e., perform tree expansion) and then refines the floorplanning/placement solution by using a simulated annealing scheme. In particular, the MB*-tree preserves the geometric relations among modules during declustering, which makes the MB*-tree an ideal data structure for the multilevel floorplanning/placement framework. Experimental results show that the MB*-tree obtains significantly better silicon area and wirelength than previous works. Further, unlike previous works, MB*-tree scales very well as the circuit size increases.
Hsun-Cheng Lee, Yao-Wen Chang, Jer-Ming Hsu, Hannah Honghua Yang
DAC3