This brief presents a fixed-point architecture based on a reconfigurable scheme for integrating several commonly used mathematical operations of speech signal processing. The proposed design can perform two transcendental mathematical operations called logarithm and powering, and three commonly used computations with similar operations named polynomial calculation, filtering, and windowing. By analyzing the adopted algorithms of the above five operations, a simplified computing unit is designed. This unit can combine six types of operations by reconfiguring the data paths, and the same multiply-add architecture can be reused for reducing the redundant usage of logic gates. The experimental results reveal that the proposed design can work at a 200-MHz clock rate, and its gate count only has 11.9k. Compared with the results of the floating-point function, the median errors of the proposed design for computing the powering and logarithmic functions are 0.57% and 0.11%, respectively. Such results indicate that this simple architecture can be effectively used in most speech processing applications.

Most authentication protocols are used for remote users, in which the registration is achieved through a secure channel and the authentication is achieved through an insecure channel. However, in real life, there are many applications in which the registration is implemented remotely through an insecure channel and the authentication is achieved through a secure channel. In this paper, a novel authentication protocol that is suitable for the insecure registration is proposed. There are three main contributions, i.e. (i) the registration can be implemented through an insecure channel, (ii) the authentication is achieved by image exchange between the registration center and the user and (iii) a proxy user authentication mechanism is proposed, which allows a proxy user to act on behalf of the primary user. The correctness and security of the proposed authentication protocol are proved by both theoretical analysis and experimental simulations.

The reference‐table‐based (RTB) steganography employs two pixels to conceal a secret digit, according to a predetermined reference table. Most of the RTB steganographic schemes discussed in the literature do not consider the non‐uniformity of the secret digits and the locating numbers indicated by the pixel pairs. In contrast, the non‐uniformity of the locating numbers exists for most of host images. When a non‐uniform secret sequence is embedded, the quality control of the stego image is quite challengeable when compared with a uniform secret sequence. To the best of the authors knowledge, most of the existing algorithms focus on the uniform sequences. In this study, they propose a multi‐round dynamic swap optimisation (MRDSO) algorithm for RTB steganography, which is more suitable for non‐uniform secret sequences. By optimising the permutation of the reference table, the proposed algorithm increases the scenarios that the locating number indicated by the pixel pair is equal to the secret digit, which means that these host pixels can carry the secret digit without any distortion. The experimental results show that the proposed MRDSO algorithm increases the quality of the stego image by 0.1–1.7 dB.

The concept of smart homes (SH) has been extensively popularized, and there are a lot of technologies that need to be continuously utilized and integrated in such a concept. In this article, some applied problems of camera array (CA) in the SH are discussed and solved. Determining how to build an effective management method for CA in order to ensure that user privacy is not encroached upon is an important issue. In SH, the applications of CA are very diversified. We suggest that a satisfactory management method of CA should be based on the open service gateway initiative (OSGi) that includes resource management and monitoring (RMM) and UPnP security for the problems of resources and privacy, respectively. Finally, an applied example of CA is addressed in an elder-care center (EC). Simulation results show that the management strategy and application of CA based on an OSGi is satisfactory.

In this study, we present a video search and indexing system based on the state support vector (SVM) network, video graph, and reinforcement agent for recognizing and organizing video events. In order to enhance the recognition performance of the state SVM network, two innovative techniques are presented: state transition correction and transition quality estimation. The classification results are also merged into the video indexing graph, which facilitates the search speed. A reinforcement algorithm with an efficient scheduling scheme significantly reduces both the power consumption and time. The experimental results show the proposed state SVM network was able to achieve a precision rate as high as 83.83% and the query results of the indexing graph reached 80% accuracy. The experiments also demonstrate the performance and feasibility of our system.

Variable block size motion estimation (VBSME) in H.264/AVC has greatly led to achieve an optimal inter frame encoding. However, the computation burden of the VBSME becomes the bottleneck of the H.264/AVC encoders. The conventional architecture in hardware realization is hard to adopt a fast software algorithm suitable to reduce the VBSME computation burden. Therefore, this paper presents a search point reduction (SPR) algorithm with an efficient hardware design, able to decrease the motion estimation time while maintaining the coding performance of H.264. The effectiveness of the proposed method is compared with those of existing methods with respect to chip area, operation frequency, and throughput rate. The proposed SPR algorithm increases the coding speed by around 90%; with a peak signal-to-noise ratio drop of less than 0.1 dB than that achieved by the JM reference software. The proposed SPR algorithm can operate at 200 MHz with 191 k gate count, which supports high-definition television 1280 720 format.

H.264/scalable video coding (SVC) has spatial scalability which can provide various resolution sequences for a single encoded bit-stream. The various resolutions can be achieved by up-sampling a lower image resolution sequence. The up-sampling method employed in H.264/SVC is directly proportional to the video quality. In order to improve the video quality with an effective up-sampling method, we propose a classified multifilter up-sampling algorithm for H.264/SVC in spatial scalability which classifies an image region as edges and nonedges. An appropriate filter is then applied to up-sample the image. In the proposed scheme, we applied the Wiener filter for edges and conventional filter for nonedges within the defined window size to preserve the edges in the up-sampled image sequence. The experimental results show that the average peak signal-to-noise ratio improvement and bit-rate reduction are 0.5 dB and 9%, respectively, which confirm that the performance of the proposed method is better than that of the existing H.264/SVC standard.

In H.264/AVC intra frame coding, the rate-distortion optimization (RDO) is employed to select the optimal coding mode to achieve the minimum rate-distortion cost. Due to a large number of combinations of coding modes, the computational burden of Rate distortion optimization (RDO) becomes extremely high in intra prediction. In this paper, we proposed an efficient intra block size decision that selects the appropriate block size for intra prediction, further proposed fast intra prediction algorithm which reduces a number of candidate modes required for RDO. Experimental results show that the proposed fast mode decision algorithm reduces the encoding time by about 68% with negligible loss of video quality.

A low complexity fast mode decision algorithm for H.264/AVC intra prediction that uses discrete cross differences (DCD) to reduce the unlikely candidate modes in the RDO calculation is proposed. By using horizontal and vertical differences in different locations, the directions of the edges can be precisely detected. Experimental results show that the proposed fast mode decision algorithm reduces the encoding time by about 56%, with negligible loss of video quality. To realize the proposed algorithm, a VLSI design, which is comprised of a cross difference unit and direction detection unit, is implemented for the mode pre-selection stage of intra prediction. The design is synthesized using UMC 0.18 mum CMOS technology and simulated with Verilog-XL. The operating frequency of the synthesized core can exceed 50 MHz.