Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Shuaibo Huang

dblp:310/8452 · DBLP profile ↗
← Back
4ranked-venue papers
3as first author
4since 2021 · last 2026
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 3 first-author · 4 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › design automation tools › accelerator design automation
accelerator design space exploration
1.012026
DCTDSE: A Bimodal Design Space Exploration Flow via Discrete-Continuous Transformation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026
Electronic design automation
design space exploration
1.012026
DCTDSE: A Bimodal Design Space Exploration Flow via Discrete-Continuous Transformation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026

Methods — techniques the papers use, named apart from their topics

predictive modeling · 1.0gradient-based optimization · 1.0discrete-continuous transformation · 1.0
YearPublicationVenuePosition
2026 DCTDSE: A Bimodal Design Space Exploration Flow via Discrete-Continuous Transformation
abstract
The conservation core accelerator presents a promising avenue for improving the computational efficiency of specific applications. However, its design space is ultra-high-dimensional, significantly increasing the exploratory effort required to identify the optimal design across performance, power, and area metrics. Furthermore, the discrete nature of the microarchitecture space renders conventional search methods ineffective. To tackle these challenges, we propose the Discrete Continuous Transformation to speedup Design Space Exploration, namely DCTDSE. It can operate in either offline or online mode. In offline mode, it transforms the original discrete design space into a continuous space, builds predictive models, performs parallel gradient-based optimization, and maps the results back to the discrete domain. In the online mode, DCTDSE refines the models by iteratively resampling previously found solutions, thereby enhancing exploration quality while maintaining moderate runtime overhead. Experimental results indicate that DCTDSE achieves a 3.9× to 40× speedup over benchmark methods in offline mode. In online mode, it provides a 2.5× speedup, with a 21% reduction in exploration quality relative to the most accurate comparison method.
Shuaibo Huang, Liangji Wu, Yuyang Ye 0001, Hao Yan 0002, Longxing Shi
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2025 An Imitation Augmented Reinforcement Learning Framework for CGRA Design Space Exploration
abstract
Coarse-Grained Reconfigurable Arrays (CGRAs) are a promising architecture that warrants thorough design space exploration (DSE). However, traditional DSE methods for CGRAs often get trapped in local optima due to singularities, i.e., invalid design points caused by CGRA mapping failures. In this paper, we propose a singularity-aware framework based on the integration of reinforcement learning (RL) and imitation learning (IL) for DSE of CGRAs. Our approach learns from both valid and invalid points, substantially reducing the probability of sampling singularities and accelerating the escape from inefficient regions, ultimately achieving high-quality Pareto points. Experimental results demonstrate that our framework improves the hypervolume (HV) of the Pareto front by 23.56% compared to state-of-the-art methods, with a comparable time overhead.
Liangji Wu, Shuaibo Huang, Shiyang Wu, Hao Yan 0002, Longxing Shi
DATE2
2025 ARS-Flow 2.0: An enhanced design space exploration flow for accelerator-rich system based on active learning
Shuaibo Huang, Yuyang Ye 0001, Hao Yan 0002, Longxing Shi
Integr.1
2024 ARS-Flow: A Design Space Exploration Flow for Accelerator-rich System based on Active Learning
abstract
Surrogate model-based design space exploration (DSE) is the mainstream method to search for optimal microarchitecture designs. However, it is hard to build accurate models for accelerator-rich systems within limited samples due to its high dimensional characteristic. Moreover, it is easy to fall into local optimal or difficult to converge. To solve these two problems, we propose a DSE flow based on active learning, namely ARS-Flow. It is featured with Pareto-region-oriented stochastic resampling method (PRSRS) and multiobjective genetic algorithm with self-adaptive hyperparameter control (SAMOGA). Taking the gem5-SALAM system for illustration, the proposed method can build more accurate models and find better microarchitecture designs with acceptable runtime costs.
Shuaibo Huang, Yuyang Ye 0001, Hao Yan 0002, Longxing Shi
ASPDAC1