Demo Data from SIGIR 2026 / reviewers in the wild / expert
Gilbert Jonatan
dblp:312/3896
· DBLP profile ↗
3ranked-venue papers
0as first author
3since 2021 · last 2025
0000-0002-3836-6353ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 3 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Hardware accelerators and domain-specific architectures · 52% Memory systems · 20% High-performance computing · 16% | |
| Artificial intelligence
1 paper |
Graph learning · 100% | |
| Network and information security
1 paper |
Cryptographic primitives and cryptanalysis · 100% |
Topics — the 10 heaviest of 10, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
High-performance computing
collective communication |
0.9 | 1 | 2025 | PIMnet: A Domain-Specific Network for Efficient Collective Communication in Scalable PIM · HPCA 2025 |
Memory systems
processing-in-memory |
0.9 | 1 | 2025 | PIMnet: A Domain-Specific Network for Efficient Collective Communication in Scalable PIM · HPCA 2025 |
Machine learning › Graph learning
graph neural network |
0.8 | 1 | 2024 | NeuraChip: Accelerating GNN Computations with a Hash-based Decoupled Spatial Accelerator · ISCA 2024 |
Hardware accelerators and domain-specific architectures › machine learning accelerator
graph neural network accelerator |
0.8 | 1 | 2024 | NeuraChip: Accelerating GNN Computations with a Hash-based Decoupled Spatial Accelerator · ISCA 2024 |
Hardware accelerators and domain-specific architectures
sparse matrix multiplication accelerator |
0.8 | 1 | 2024 | NeuraChip: Accelerating GNN Computations with a Hash-based Decoupled Spatial Accelerator · ISCA 2024 |
Hardware accelerators and domain-specific architectures
cryptographic accelerator |
0.7 | 1 | 2023 | GME: GPU-based Microarchitectural Extensions to Accelerate Homomorphic Encryption · MICRO 2023 |
GPUs and heterogeneous computing
GPU computing |
0.7 | 1 | 2023 | GME: GPU-based Microarchitectural Extensions to Accelerate Homomorphic Encryption · MICRO 2023 |
Hardware accelerators and domain-specific architectures › cryptographic accelerator
homomorphic encryption accelerator |
0.7 | 1 | 2023 | GME: GPU-based Microarchitectural Extensions to Accelerate Homomorphic Encryption · MICRO 2023 |
Memory systems › memory management
on-chip memory management |
0.2 | 1 | 2024 | NeuraChip: Accelerating GNN Computations with a Hash-based Decoupled Spatial Accelerator · ISCA 2024 |
Cryptographic primitives and cryptanalysis › homomorphic encryption
fully homomorphic encryption |
0.2 | 1 | 2023 | GME: GPU-based Microarchitectural Extensions to Accelerate Homomorphic Encryption · MICRO 2023 |
Methods — techniques the papers use, named apart from their topics
hash-based mapping · 1.5gustavson's algorithm · 1.5cycle-accurate simulation · 1.5GPU microarchitectural extension · 1.3UPMEM characterization · 0.9
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | PIMnet: A Domain-Specific Network for Efficient Collective Communication in Scalable PIMabstractProcessing-in-memory (PIM), where compute is moved closer to memory or data, has been explored to accelerate emerging workloads. Different PIM-based systems have been announced, each offering a unique microarchitectural organization of their compute units, ranging from fixed functional units to programmable general-purpose compute cores near memory. However, one fundamental limitation of PIM is that each compute unit can only access its local memory; access to “remote” memory must occur through the host CPU - potentially limiting application performance scalability. In this work, we first characterize the scalability of real PIM architectures using the UPMEM PIM system. We analyze how the overhead of communicating through the host (instead of providing direct communication between the PIM compute units) can become a bottleneck for collective communications that are commonly used in many workloads. To overcome this inter-PIM bank communication, we propose PIMnet - a PIM interconnection network for PIM banks that provides direct connectivity between compute units and removes the overhead of communicating through the host. PIMnet exploits bandwidth parallelism where communication across the different PIM bank/chips can occur in parallel to maximize communication performance. PIMnet also matches the DRAM packaging hierarchy with a multi-tier network architecture. Unlike traditional interconnection networks, PIMnet is a PIMcontrolled network where communication is managed by the PIM logic, optimizing collective communications and minimizing the hardware overhead of PIMnet. Our evaluation of PIMnet shows that it provides up to $85 \times$ speedup on collective communications and achieves a $11.8 \times$ improvement on real applications compared to the baseline PIM. Hyojun Son, Gilbert Jonatan, Haeyoon Cho 0002, Kaustubh Shivdikar, José L. Abellán, Ajay Joshi, David R. Kaeli, John Kim 0001 |
HPCA | 2 |
| 2024 | NeuraChip: Accelerating GNN Computations with a Hash-based Decoupled Spatial AcceleratorabstractGraph Neural Networks (GNNs) are emerging as a formidable tool for processing non-euclidean data across various domains, ranging from social network analysis to bioinformatics. Despite their effectiveness, their adoption has not been pervasive because of scalability challenges associated with large-scale graph datasets, particularly when leveraging message passing. They exhibit irregular sparsity patterns, resulting in unbalanced compute resource utilization. Prior accelerators investigating Gustavson’s technique adopted look-ahead buffers for prefetching data, aiming to prevent compute stalls. However, these solutions lead to inefficient use of the on-chip memory, leading to redundant data residing in cache.To tackle these challenges, we introduce NeuraChip, a novel GNN spatial accelerator based on Gustavson’s algorithm. NeuraChip decouples the multiplication and addition computations in sparse matrix multiplication. This separation allows for independent exploitation of their unique data dependencies, facilitating efficient resource allocation. We introduce a rolling eviction strategy to mitigate data idling in on-chip memory as well as address the prevalent issue of memory bloat in sparse graph computations. Furthermore, the compute resource load balancing is achieved through a dynamic reseeding hash-based mapping, ensuring uniform utilization of computing resources agnostic of sparsity patterns. Finally, we present NeuraSim, an open-source, cycle-accurate, multi-threaded, modular simulator for comprehensive performance analysis.Overall, NeuraChip presents a significant improvement, yielding an average speedup of $22.1 \times$ over Intel’s MKL, $17.1 \times$ over NVIDIA’s cuSPARSE, $16.7 \times$ over AMD’s hipSPARSE, and $1.5 \times$ over prior state-of-the-art SpGEMM accelerator and $1.3 \times$ over GNN accelerator. The source code for our open-sourced simulator and performance visualizer is publicly accessible on GitHub1. CCS CONCEPTS • Computer systems organization → Multicore architectures; Interconnection architectures; • Computing methodologies → Neural networks; • Theory of computation → Graph algorithms analysis; • Hardware → Hardware accelerators.1https://github.com/NeuraChip/neurachip Kaustubh Shivdikar, Nicolas Bohm Agostini, Malith Jayaweera, Gilbert Jonatan, José L. Abellán, Ajay Joshi, John Kim 0001, David R. Kaeli |
ISCA | 4 |
| 2023 | GME: GPU-based Microarchitectural Extensions to Accelerate Homomorphic EncryptionabstractFully Homomorphic Encryption (FHE) enables the processing of encrypted data without decrypting it. FHE has garnered significant attention over the past decade as it supports secure outsourcing of data processing to remote cloud services. Despite its promise of strong data privacy and security guarantees, FHE introduces a slowdown of up to five orders of magnitude as compared to the same computation using plaintext data. This overhead is presently a major barrier to the commercial adoption of FHE. Kaustubh Shivdikar, Yuhui Bao, Rashmi S. Agrawal 0001, Michael Tian Shen, Gilbert Jonatan, Evelio Mora, Alexander Ingare, Neal Livesay, José L. Abellán, John Kim 0001, Ajay Joshi, David R. Kaeli |
MICRO | 5 |