A design methodology for the implementation of multi-million gate system-on-chip designs is described. The new methodology is based on the creation of a silicon virtual prototype early in the back-end design process. The prototype is generated in a fraction of the time required to complete the traditional back-end flow but still maintains very high correlation with the final design. The physical prototype becomes the 'cockpit' where many design implementation decisions can be optimized by leveraging the short iteration times. Hierarchical design methodologies benefit from the prototyping stage by enabling a more optimal partitioning. The silicon virtual prototype also alters the nature of the hand-off model between front-end and back-end designers. The netlist can now be quickly validated using the prototype: the physical reality is being injected early in the design process resulting in fewer iterations between front-end and back-end.

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Logic emulation systems based on FPGAs are becoming a widely accepted solution for the verification of large, complex designs. However, the acceptance of this technology is still lagging for the verification of ASIC designs with 50,000 gates or less of custom logic. This paper presents Project Spinnaker, a project aimed at the development of a rapid prototyping solution for this market segment. The project emphasizes what are believed to be the three key aspects for broadening the acceptance of the emulation verification methodology among ASIC designers: speed, cost, and automation.>