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Andrew Sica

dblp:321/4355 · DBLP profile ↗
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2ranked-venue papers
0as first author
2since 2021 · last 2023
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 44% Processor architecture and microarchitecture · 44% Cloud and datacenter computing · 13%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures
machine learning accelerator		 0.612022
AI accelerator on IBM telum processor: industrial product · ISCA 2022
Processor architecture and microarchitecture › microprocessor
server processor		 0.612022
AI accelerator on IBM telum processor: industrial product · ISCA 2022

Methods — techniques the papers use, named apart from their topics

on-chip acceleration · 0.6
YearPublicationVenuePosition
2023 Acceleration of Decision-Tree Ensemble Models on the IBM Telum Processor
abstract
This paper presents a tensor-based algorithm that leverages a hardware accelerator for inferencing decision-tree-based machine learning models. The algorithm has been integrated in a public software library and is demonstrated on an IBM z16 server, using the Telum processor with the Integrated Accelerator for AI. We describe the architecture and implementation of the algorithm and present experimental results that demonstrate its superior runtime performance compared with popular CPU-based machine learning inference implementations.
Nikolaos Papandreou, Jan van Lunteren, Andreea Anghel, Thomas P. Parnell, Martin Petermann, Milos Stanisavljevic, Cédric Lichtenau, Andrew Sica, Dominic Röhm, Elpida Tzortzatos, Haralampos Pozidis
 ISCAS8
2022 AI accelerator on IBM telum processor: industrial product
abstract
IBM Telum is the next generation processor chip for IBM Z and LinuxONE systems. The Telum design is focused on enterprise class workloads and it achieves over 40% per socket performance growth compared to IBM z15. The IBM Telum is the first server-class chip with a dedicated on-chip AI accelerator that enables clients to gain real time insights from their data as it is getting processed.
Cédric Lichtenau, Alper Buyuktosunoglu, Ramon Bertran Monfort, Peter Figuli, Christian Jacobi 0002, Nikolaos Papandreou, Haralampos Pozidis, Anthony Saporito, Andrew Sica, Elpida Tzortzatos
 ISCA9