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Zhenlin Qi

dblp:323/0852 · DBLP profile ↗
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6ranked-venue papers
3as first author
6since 2021 · last 2026
0000-0001-8838-6064ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 3 first-author · 4 since 2021Databases, data management, data science and information retrieval · 2 · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
5 papers
Memory systems · 75% Storage systems · 25%
Databases, data mining, and information retrieval
2 papers
Indexing and storage engines · 100%

Topics — the 15 heaviest of 16, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
non-volatile memory
1.632024
Exploiting Persistent CPU Cache for Scalable Persistent Hash Index · ICDE 2024
NBTree: a Lock-free PM-friendly Persistent B+-Tree for eADR-enabled PM Systems · Proc. VLDB Endow. 2022
Revisiting PM-Based B+-Tree With Persistent CPU Cache · IEEE Trans. Parallel Distributed Syst. 2024
Memory systems › non-volatile memory › persistent memory
persistent memory indexing
1.522024
Revisiting PM-Based B+-Tree With Persistent CPU Cache · IEEE Trans. Parallel Distributed Syst. 2024
Exploiting Persistent CPU Cache for Scalable Persistent Hash Index · ICDE 2024
Storage systems › file systems
distributed file system
1.012026
SwitchFS: Exploiting Persistent Memory Bandwidth in Cluster via Learning-based I/O Path Selection · ACM Trans. Archit. Code Optim. 2026
Memory systems › non-volatile memory
persistent memory
1.012026
SwitchFS: Exploiting Persistent Memory Bandwidth in Cluster via Learning-based I/O Path Selection · ACM Trans. Archit. Code Optim. 2026
Memory systems
hybrid memory
0.912025
Chrono: Meticulous Hotness Measurement and Flexible Page Migration for Memory Tiering · EuroSys 2025
Memory systems › virtual memory management
page migration
0.912025
Chrono: Meticulous Hotness Measurement and Flexible Page Migration for Memory Tiering · EuroSys 2025
Memory systems
tiered memory
0.912025
Chrono: Meticulous Hotness Measurement and Flexible Page Migration for Memory Tiering · EuroSys 2025
Indexing and storage engines
hash index
0.812024
Exploiting Persistent CPU Cache for Scalable Persistent Hash Index · ICDE 2024
Indexing and storage engines › hash index
persistent memory hash index
0.812024
Exploiting Persistent CPU Cache for Scalable Persistent Hash Index · ICDE 2024
Storage systems › indexing
persistent b+-tree
0.812024
Revisiting PM-Based B+-Tree With Persistent CPU Cache · IEEE Trans. Parallel Distributed Syst. 2024
Indexing and storage engines › b+-tree
persistent b+-tree
0.612022
NBTree: a Lock-free PM-friendly Persistent B+-Tree for eADR-enabled PM Systems · Proc. VLDB Endow. 2022
Indexing and storage engines › persistent data structure
persistent index
0.612022
NBTree: a Lock-free PM-friendly Persistent B+-Tree for eADR-enabled PM Systems · Proc. VLDB Endow. 2022
Datacenter networks
RDMA
0.312026
SwitchFS: Exploiting Persistent Memory Bandwidth in Cluster via Learning-based I/O Path Selection · ACM Trans. Archit. Code Optim. 2026
Storage systems
crash consistency
0.212024
Exploiting Persistent CPU Cache for Scalable Persistent Hash Index · ICDE 2024
Indexing and storage engines › concurrent index
latch-free index
0.212022
NBTree: a Lock-free PM-friendly Persistent B+-Tree for eADR-enabled PM Systems · Proc. VLDB Endow. 2022

Methods — techniques the papers use, named apart from their topics

reinforcement learning · 2.0model-driven opportunistic replication · 2.0fine-grained concurrency control · 2.0log-structured insert · 1.9page classification · 0.9hotness measurement · 0.9two-phase concurrency protocol · 0.8sync-on-write · 0.8sync-on-read · 0.8shift-aware search · 0.8hardware transactional memory · 0.8extendible hashing · 0.8cooperative SMO · 0.8lock-free synchronization · 0.6atomic primitives · 0.6
YearPublicationVenuePosition
2026 SwitchFS: Exploiting Persistent Memory Bandwidth in Cluster via Learning-based I/O Path Selection
abstract
Persistent Memory (PM) and Remote Direct Memory Access (RDMA) technologies have significantly improved the storage and network performance in data centers and spawned a slew of distributed file systems (DFS) designs. Existing DFSs often consider remote storage a performance constraint, assuming it delivers lower bandwidth and higher latency than local devices. However, the advancements in RDMA technology present an opportunity to narrow the performance disparity between local and remote access, empowering DFSs to harness both local and remote I/O capabilities, thereby attaining higher aggregated throughput. We propose SwitchFS, a new DFS architecture that exploits all the available PM bandwidth in a cluster with generative I/O path assignment policy. It dynamically steers client-side I/O requests to the local cache and the remote devices accessible through RDMA network. To determine the run-time I/O path adaptively, we introduce MELON, an I/O path selection policy based on a reinforcement learning model, designed to optimize expected I/O latency. Meanwhile, SwitchFS adopts a model-driven opportunistic replication mechanism at the server-side, which further improves I/O bandwidth utilization of remote devices across the cluster. Furthermore, we adopt the fine-grained concurrency control approach to improve scalability. Across synthetic and real-world application workloads, SwitchFS improves throughput by up to 5.9× over existing DFS designs while preserving low tail latency and incurring modest learning overhead.
Zhenlin Qi, Shengan Zheng, Bowen Zhang 0012, Linpeng Huang
ACM Trans. Archit. Code Optim.1
2025 Chrono: Meticulous Hotness Measurement and Flexible Page Migration for Memory Tiering
abstract
As the memory demand continues to surge, the limitations of DRAM scalability have spurred the development of various new memory technologies in today's data centers. In order to harness the benefits of the heterogeneous memory architecture, tiering has become a widely adopted memory management paradigm. The effectiveness of a tiered memory management system primarily relies on its ability to accurately identify frequently accessed ("hot") pages and infrequently accessed ("cold") pages, and efficiently relocate them between tiers. However, existing systems rely on coarse-grained frequency measurement schemes that do not align with the performance characteristics of modern memory devices and memory-intensive applications. Additionally, these systems often incorporate rigid rules or manually configured parameters for page classification, resulting in inflexible migration strategies.
Zhenlin Qi, Shengan Zheng, Yifeng Hui, Bowen Zhang 0012, Linpeng Huang, Hong Mei 0001
EuroSys1
2024 Exploiting Persistent CPU Cache for Scalable Persistent Hash Index
abstract
Byte-addressable persistent memory (PM) has been widely studied in the past few years. Recently, the emerging eADR technology further incorporates CPU cache into the persistence domain. The persistent CPU cache is promising to optimize the write performance of PM-based storage systems and facilitate the design of concurrent crash-consistent data structures. In this paper, we propose Spash, a highly scalable persistent hash index for PM systems with persistent CPU cache. Spash fully exploits the benefits of persistent CPU cache to implement a durable linearizable index with low PM access overhead and high concurrency. Spash employs a fine-grained extendible hash architecture and a metadata-free segment design to minimize the number of PM accesses. Moreover, Spash adopts adaptive in-place updates and compacted-flush insertions, which dramatically conserve scarce PM write bandwidth by absorbing a large amount of PM write in the persistent CPU cache. Furthermore, Spash proposes a two-phase concurrency protocol and a collaborative staged doubling mechanism, which leverage the persistent CPU cache and hardware transactional memory to achieve lock-free concurrency and durable linearizability. Spash outperforms the other state-of-the-art persistent hash indexes in YCSB workloads by up to 19.6×.
Bowen Zhang 0012, Shengan Zheng, Liangxu Nie, Zhenlin Qi, Linpeng Huang, Hong Mei 0001
ICDE4
2024 Revisiting PM-Based B+-Tree With Persistent CPU Cache
abstract
Persistent memory (PM) promises near-DRAM performance as well as data persistence. Recently, a new feature called eADR is available for PM-equipped platforms to guarantee the persistence of CPU cache. The emergence of eADR presents unique opportunities to build lock-free data structures and unleash the full potential of PM. In this paper, we propose NBTree, a lock-free PM-friendly B$^+$-Tree, to deliver high scalability and low PM overhead. To our knowledge, NBTree is the first persistent index designed for PM systems with persistent CPU cache. To achieve lock-free, NBTree uses atomic primitives to serialize index operations. Moreover, NBTree proposes five novel techniques to enable lock-free accesses during structural modification operations (SMO), includingthree-phase SMO,sync-on-write,sync-on-read,cooperative SMO, andshift-aware search. To reduce PM access overhead, NBTree employs a decoupled leaf node design to absorb the metadata accesses in DRAM. Moreover, NBTree devises a cache-crafty persistent allocator and adoptslog-structured insertandin-place update/deleteto enhance the access locality of write operations, absorbing a substantial amount of PM writes in persistent CPU cache. Our evaluation shows that NBTree achieves up to 11× higher throughput and 43× lower 99% tail latency than state-of-the-art persistent B$^+$-Trees under YCSB workloads.
Bowen Zhang 0012, Shengan Zheng, Liangxu Nie, Zhenlin Qi, Linpeng Huang, Hong Mei 0001
IEEE Trans. Parallel Distributed Syst.4
2023 Conflux: Exploiting Persistent Memory and RDMA Bandwidth via Adaptive I/O Mode Selection
abstract
Persistent Memory (PM) and Remote Direct Memory Access (RDMA) technologies have significantly improved the storage and network performance in data centers and spawned a slew of distributed file system (DFS) designs. Existing DFSs often consider remote storage a performance constraint, assuming it delivers lower bandwidth and higher latency than local storage devices. However, the advances in RDMA technology provide an opportunity to bridge the performance gap between local and remote access, enabling DFSs to leverage both local and remote PM bandwidth and achieve higher overall throughput.
Zhenlin Qi, Shengan Zheng, Yifeng Hui, Bowen Zhang 0012, Linpeng Huang
ICPP1
2022 NBTree: a Lock-free PM-friendly Persistent B+-Tree for eADR-enabled PM Systems
abstract
Persistent memory (PM) promises near-DRAM performance as well as data persistency. Recently, a new feature called eADR is available on the 2 nd generation Intel Optane PM with the 3 rd generation Intel Xeon Scalable Processors. eADR ensures that data stored within the CPU caches will be flushed to PM upon the power failure. Thus, in eADR-enabled PM systems, the globally visible data is considered persistent, and explicit data flushes are no longer necessary. The emergence of eADR presents unique opportunities to build lock-free data structures and unleash the full potential of PM. In this paper, we propose NBTree, a lock-free PM-friendly B + -Tree, to deliver high scalability and low PM overhead. To our knowledge, NBTree is the first persistent index designed for eADR-enabled PM systems. To achieve lock-free, NBTree uses atomic primitives to serialize leaf node operations. Moreover, NBTree proposes four novel techniques to enable lock-free access to the leaf during structural modification operations (SMO), including three-phase SMO, sync-on-write, sync-on-read , and cooperative SMO. For inner node operations, we develop a shift-aware search algorithm to resolve read-write conflicts. To reduce PM overhead, NBTree decouples the leaf nodes into a metadata layer and a key-value layer. The metadata layer is stored in DRAM, along with the inner nodes, to reduce PM accesses. NBTree also adopts log-structured insert and in-place update/delete to improve cache utilization. Our evaluation shows that NBTree achieves up to 11X higher throughput and 43X lower 99% tail latency than state-of-the-art persistent B + -Trees under YCSB workloads.
Bowen Zhang 0012, Shengan Zheng, Zhenlin Qi, Linpeng Huang
Proc. VLDB Endow.3