Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Benjamin Lienhard

dblp:325/9810 · DBLP profile ↗
← Back
4ranked-venue papers
0as first author
4since 2021 · last 2025
0000-0001-5241-4131ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 4 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Emerging computing paradigms · 56% Hardware accelerators and domain-specific architectures · 28% Reconfigurable computing and FPGAs · 16%
Theoretical computer science
2 papers
Quantum computing and quantum information · 100%
Artificial intelligence
1 paper
Efficient and distributed learning · 100%

Topics — the 7 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Emerging computing paradigms
quantum computer architecture
1.522025
Efficient and Scalable Architectures for Multi-level Superconducting Qubit Readout · DAC 2025
Scaling Qubit Readout with Hardware Efficient Machine Learning Architectures · ISCA 2023
Emerging computing paradigms › quantum computing and quantum information › quantum measurement
superconducting qubit readout
1.522025
Efficient and Scalable Architectures for Multi-level Superconducting Qubit Readout · DAC 2025
Scaling Qubit Readout with Hardware Efficient Machine Learning Architectures · ISCA 2023
Reconfigurable computing and FPGAs
FPGA implementation
0.912025
KLiNQ: Knowledge Distillation-Assisted Lightweight Neural Network for Qubit Readout on FPGA · DAC 2025
Quantum computing and quantum information
quantum error correction
0.912025
Efficient and Scalable Architectures for Multi-level Superconducting Qubit Readout · DAC 2025
Hardware accelerators and domain-specific architectures
machine learning accelerator
0.712023
Scaling Qubit Readout with Hardware Efficient Machine Learning Architectures · ISCA 2023
Machine learning › Efficient and distributed learning › model compression
knowledge distillation
0.312025
KLiNQ: Knowledge Distillation-Assisted Lightweight Neural Network for Qubit Readout on FPGA · DAC 2025
Machine learning › Efficient and distributed learning
model compression
0.312025
KLiNQ: Knowledge Distillation-Assisted Lightweight Neural Network for Qubit Readout on FPGA · DAC 2025

Methods — techniques the papers use, named apart from their topics

neural network · 4.4knowledge distillation · 2.6matched filter · 1.7FPGA · 1.7machine learning · 0.7
YearPublicationVenuePosition
2025 KLiNQ: Knowledge Distillation-Assisted Lightweight Neural Network for Qubit Readout on FPGA
abstract
Superconducting qubits are among the most promising candidates for building quantum information processors. Yet, they are often limited by slow and error-prone qubit readout-a critical factor in achieving high-fidelity operations. While current methods, including deep neural networks, enhance readout accuracy, they typically lack support for mid-circuit measurements essential for quantum error correction, and they usually rely on large, resource-intensive network models. This paper presents KLiNQ, a novel qubit readout architecture leveraging lightweight neural networks optimized via knowledge distillation. Our approach achieves around a $99 \%$ reduction in model size compared to the baseline while maintaining a qubitstate discrimination accuracy of $91 \%$. KLiNQ facilitates rapid, independent qubit-state readouts that enable mid-circuit measurements by assigning a dedicated, compact neural network for each qubit. Implemented on the Xilinx UltraScale+ FPGA, our design can perform the discrimination within 32 ns. The results demonstrate that compressed neural networks can maintain highfidelity independent readout while enabling efficient hardware implementation, advancing practical quantum computing.
Xiaorang Guo, Tigran Bunarjyan, Dai Liu, Benjamin Lienhard, Martin Schulz 0001
DAC4
2025 Efficient and Scalable Architectures for Multi-level Superconducting Qubit Readout
abstract
Realizing the full potential of quantum computing requires large-scale quantum computers capable of running quantum error correction (QEC) to mitigate hardware errors and maintain quantum data coherence. While quantum computers operate within a two-level computational subspace, many processor modalities are inherently multi-level systems. This leads to occasional leakage into energy levels outside the computational subspace, complicating error detection and undermining QEC protocols. The problem is particularly severe in engineered qubit devices like superconducting transmons, a leading technology for fault-tolerant quantum computing. Addressing this challenge requires effective multi-level quantum system readout to identify and mitigate leakage errors. We propose a scalable, high-fidelity three-level readout that reduces FPGA resource usage by $60 \times$ compared to the baseline while reducing readout time by $20 \%$, enabling faster leakage detection. By employing matched filters to detect relaxation and excitation error patterns and integrating a modular lightweight neural network to correct crosstalk errors, the protocol significantly reduces hardware complexity, achieving a $100 \times$ reduction in neural network size. Our design supports efficient, real-time implementation on off-the-shelf FPGAs, delivering a $6.6 \%$ relative improvement in readout accuracy over the baseline. This innovation enables faster leakage mitigation, enhances QEC reliability, and accelerates the path toward faulttolerant quantum computing.
Chaithanya Naik Mude, Satvik Maurya, Benjamin Lienhard, Swamit S. Tannu
DAC3
2025 Qubit-State Discrimination using Neural Networks with Rapid and Energy-Efficient Compute Arrays
abstract
Neural networks (NNs) implemented on field-programmable gate arrays (FPGAs) provide fast, high-fidelity solutions for processing readout signals from quantum information processors. However, application-specific integrated circuits (ASICs) instead of FPGAs hold the potential for improved performance, a largely unexplored path. This work proposes specialized hardware for NN-based qubit-state discrimination. We optimize the NN architecture to minimize resource requirements by reducing the layer width, employing linear activation functions, and weight quantization. Quantization-aware training is used to preserve accuracy despite these optimizations. Next, a compute array employing output stationary dataflow is chosen to process the NN workload. The compute array with abundant multipliers and adders can complete one NN inference in 63 ns, which makes it a good candidate for real-time qubit-state discrimination.
Yuntian Liu, Yi Sheng Chong, Benjamin Lienhard, Minghao Fan, Wang Ling Goh, Vishnu P. Nambiar, Anh-Tuan Do
ISCAS3
2023 Scaling Qubit Readout with Hardware Efficient Machine Learning Architectures
abstract
Reading a qubit is a fundamental operation in quantum computing. It translates quantum information into classical information enabling subsequent classification to assign the qubit states '0' or '1'. Unfortunately, qubit readout is one of the most error-prone and slowest operations on a superconducting quantum processor. On state-of-the-art superconducting quantum processors, readout errors can range from 1--10%. These errors occur for various reasons - crosstalk, spontaneous state transitions, and excitation caused by the readout pulse. The error-prone nature of readout has resulted in significant research to design better discriminators to achieve higher qubit-readout accuracies. High readout accuracy is essential for enabling high fidelity for near-term noisy quantum computers and error-corrected quantum computers of the future.
Satvik Maurya, Chaithanya Naik Mude, William D. Oliver, Benjamin Lienhard, Swamit S. Tannu
ISCA4