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Abdul Rafae Noor

dblp:329/0305 · DBLP profile ↗
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4ranked-venue papers
1as first author
4since 2021 · last 2025
0000-0002-9979-3252ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 4 · 1 first-author · 4 since 2021Systems, architecture and hardware · 2 · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Software engineering, system software, and programming languages
4 papers
Compilers and program optimization · 62% Program synthesis and code generation · 16% Software maintenance and evolution · 10%
Computer architecture, parallel and distributed computing, and storage systems
3 papers
Hardware accelerators and domain-specific architectures · 61% GPUs and heterogeneous computing · 39%

Topics — the 12 heaviest of 13, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Compilers and program optimization › code generation
instruction selection
1.622025
MISAAL: Synthesis-Based Automatic Generation of Efficient and Retargetable Semantics-Driven Optimizations · Proc. ACM Program. Lang. 2025
Hydride: A Retargetable and Extensible Synthesis-based Compiler for Modern Hardware Architectures · ASPLOS (2) 2024
Compilers and program optimization
intermediate representation
1.022025
Hydride: A Retargetable and Extensible Synthesis-based Compiler for Modern Hardware Architectures · ASPLOS (2) 2024
HPVM-HDC: A Heterogeneous Programming System for Accelerating Hyperdimensional Computing · ISCA 2025
Program synthesis and code generation
rewrite rule inference
0.912025
MISAAL: Synthesis-Based Automatic Generation of Efficient and Retargetable Semantics-Driven Optimizations · Proc. ACM Program. Lang. 2025
Hardware accelerators and domain-specific architectures › neural network hardware › brain-inspired computing accelerator
hyperdimensional computing accelerator
0.912025
HPVM-HDC: A Heterogeneous Programming System for Accelerating Hyperdimensional Computing · ISCA 2025
Compilers and program optimization › compiler construction
retargetable compilation
0.812024
Hydride: A Retargetable and Extensible Synthesis-based Compiler for Modern Hardware Architectures · ASPLOS (2) 2024
Software maintenance and evolution › software reengineering
software debloating
0.612022
Trimmer: An Automated System for Configuration-Based Software Debloating · IEEE Trans. Software Eng. 2022
Programming languages and type systems
domain-specific languages
0.312025
HPVM-HDC: A Heterogeneous Programming System for Accelerating Hyperdimensional Computing · ISCA 2025
Hardware accelerators and domain-specific architectures
tensor accelerator
0.312025
MISAAL: Synthesis-Based Automatic Generation of Efficient and Retargetable Semantics-Driven Optimizations · Proc. ACM Program. Lang. 2025
Hardware accelerators and domain-specific architectures
domain-specific compilers
0.212024
Hydride: A Retargetable and Extensible Synthesis-based Compiler for Modern Hardware Architectures · ASPLOS (2) 2024
Systems and software security
attack surface reduction
0.212022
Trimmer: An Automated System for Configuration-Based Software Debloating · IEEE Trans. Software Eng. 2022
Program analysis › data flow analysis
constant propagation
0.212022
Trimmer: An Automated System for Configuration-Based Software Debloating · IEEE Trans. Software Eng. 2022
Program analysis
static analysis
0.212022
Trimmer: An Automated System for Configuration-Based Software Debloating · IEEE Trans. Software Eng. 2022

Methods — techniques the papers use, named apart from their topics

term rewriting · 1.7reduction perforation · 1.7program synthesis · 1.7formal semantics · 1.7automatic binarization · 1.7synthesis-based compilation · 1.5pseudocode specification · 1.5sparse constant propagation · 1.1inter-procedural constant propagation · 1.1dead code elimination · 1.1
YearPublicationVenuePosition
2025 HPVM-HDC: A Heterogeneous Programming System for Accelerating Hyperdimensional Computing
abstract
Hyperdimensional Computing (HDC), a technique inspired by cognitive models of computation, has been proposed as an efficient and robust alternative basis for machine learning.HDC programs are often manually written in low-level and target specific languages targeting CPUs, GPUs, and FPGAs-these codes cannot be easily retargeted onto HDC-specific accelerators.No previous programming system enables productive development of HDC programs and generates efficient code for several hardware targets.We propose a heterogeneous programming system for HDC: a novel programming language, HDC++, for writing applications using a unified programming model, including HDC-specific primitives to improve programmability, and a heterogeneous compiler, HPVM-HDC, that provides an intermediate representation for compiling HDC programs to many hardware targets.We implement two tuning optimizations, automatic binarization and reduction perforation, that exploit the error resilient nature of HDC.Our evaluation shows that HPVM-HDC generates performance-competitive code for CPUs and GPUs, achieving a geomean speed-up of 1.17x over optimized baseline CUDA implementations with a geomean * Equally contributing authors.
Russel Arbore, Xavier Routh, Abdul Rafae Noor, Akash Kothari, Haichao Yang, Sumukh Pinge, Minxuan Zhou, Tajana Rosing, Vikram S. Adve
ISCA3
2025 MISAAL: Synthesis-Based Automatic Generation of Efficient and Retargetable Semantics-Driven Optimizations
abstract
Using program synthesis to select instructions for and optimize input programs is receiving increasing attention. However, existing synthesis-based compilers are faced by two major challenges that prohibit the deployment of program synthesis in production compilers: exorbitantly long synthesis times spanning several minutes and hours; and scalability issues that prevent synthesis of complex modern compute and data swizzle instructions, which have been found to maximize performance of modern tensor and stencil workloads. This paper proposes Misaal , a synthesis-based compiler that employs a novel strategy to use formal semantics of hardware instructions to automatically prune a large search space of rewrite rules for modern complex instructions in an offline stage. Misaal also proposes a novel methodology to make term-rewriting process in the online stage (at compile-time) extremely lightweight so as to enable programs to compile in seconds. Our results show that Misaal reduces compilation times by up to a geomean of 16x compared to the state-of-theart synthesis-based compiler, Hydride . Misaal also delivers competitive runtime performance against the production compiler for image processing and deep learning workloads, Halide, as well as Hydride across x86, Hexagon and ARM.
Abdul Rafae Noor, Dhruv Baronia, Akash Kothari, Muchen Xu, Charith Mendis, Vikram S. Adve
Proc. ACM Program. Lang.1
2024 Hydride: A Retargetable and Extensible Synthesis-based Compiler for Modern Hardware Architectures
abstract
As modern hardware architectures evolve to support increasingly diverse, complex instruction sets for meeting the performance demands of modern workloads in image processing, deep learning, etc., it has become ever more crucial for compilers to provide robust support for evolution of their internal abstractions and retargetable code generation support to keep pace with emerging instruction sets. We propose Hydride, a novel approach to compiling for complex, emerging hardware architectures. Hydride uses vendor-defined pseudocode specifications of multiple hardware ISAs to automatically design retargetable instructions for AutoLLVM IR, an extensible compiler IR which consists of (formally defined) language-independent and target-independent LLVM IR instructions to compile to those ISAs, and automatically generated instruction selection passes to lower AutoLLVM IR to each of the specified hardware ISAs. Hydride also includes a code synthesizer that automatically generates code generation support for schedule-based languages, such as Halide, to optimally generate AutoLLVM IR. Our results show that Hydride is able to represent 3,557 instructions combined in x86, Hexagon, ARM architectures using only 397 AutoLLVM IR instructions, including (Intel) SSE2, SSE4, AVX, AVX2, AVX512, (Qualcomm) Hexagon HVX, and (ARM) NEON vector ISAs. We created a new Halide compiler with Hydride using only a formal semantics of Halide IR, leveraging the auto-generated AutoLLVM IR and back-ends for the three hardware architectures. Across kernels from deep learning and image processing, this compiler is able to perform just as well as the mature, production Halide compiler on Hexagon, and outperform on x86 by 8% and ARM by 3%. Hydride also outperforms the production Halide's LLVM back end by 12% on x86, 100% on HVX, and 26% on ARM across the same kernels.
Akash Kothari, Abdul Rafae Noor, Muchen Xu, Hassam Uddin, Dhruv Baronia, Stefanos Baziotis, Vikram S. Adve, Charith Mendis, Sudipta Sengupta
ASPLOS (2)2
2022 Trimmer: An Automated System for Configuration-Based Software Debloating
abstract
Software bloat has negative implications for security, reliability, and performance. To counter bloat, we proposeTrimmer, a static analysis-based system for pruning unused functionality.Trimmerremoves code that is unused with respect to user-provided command-line arguments and application-specific configuration files.Trimmeruses concrete memory tracking and a custom inter-procedural constant propagation analysis that facilitates dead code elimination. Our system supports both context-sensitive and context-insensitive constant propagation. We show that context-sensitive constant propagation is important for effective software pruning in most applications. We introducesparse constant propagationthat performs constant propagation only for configuration-hosting variables and show that it performs better (higher code size reductions) compared to constant propagation for all program variables. Overall, our results show thatTrimmerreduces binary sizes for real-world programs with reasonable analysis times. Across 20 evaluated programs, we observe a mean binary size reduction of 22.7 percent and a maximum reduction of 62.7 percent. For 5 programs, we observe performance speedups ranging from 5 to 53 percent. Moreover, we show that winnowing software applications can reduce the program attack surface by removing code that contains exploitable vulnerabilities. We find that debloating usingTrimmerremoves CVEs in 4 applications.
Aatira Anum Ahmad, Abdul Rafae Noor, Hashim Sharif, Usama Hameed, Shoaib Asif, Mubashir Anwar, Ashish Gehani, Fareed Zaffar, Junaid Haroon Siddiqui
IEEE Trans. Software Eng.2