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Yoshifumi Takamoto

dblp:33/5965 · DBLP profile ↗
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6ranked-venue papers
0as first author
0since 2021 · last 2004
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3Databases, data management, data science and information retrieval · 2Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 55% Embedded and real-time systems · 43% Hardware accelerators and domain-specific architectures · 2%
Databases, data mining, and information retrieval
1 paper
Database system architecture and tuning · 100%

Topics — the 7 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
hardware/software co-design
0.012004
A Flexible and High-Reliable HW/SW Co-Design Method for Real-Time Embedded Systems · RTSS 2004
Electronic design automation › system-level design
part selection
0.012004
A Flexible and High-Reliable HW/SW Co-Design Method for Real-Time Embedded Systems · RTSS 2004
Embedded and real-time systems
real-time embedded systems
0.012004
A Flexible and High-Reliable HW/SW Co-Design Method for Real-Time Embedded Systems · RTSS 2004
Embedded and real-time systems
timing constraints
0.012004
A Flexible and High-Reliable HW/SW Co-Design Method for Real-Time Embedded Systems · RTSS 2004
Electronic design automation
hardware verification and test
0.012004
A Flexible and High-Reliable HW/SW Co-Design Method for Real-Time Embedded Systems · RTSS 2004
Electronic design automation
model checking
0.012004
A Flexible and High-Reliable HW/SW Co-Design Method for Real-Time Embedded Systems · RTSS 2004
Hardware accelerators and domain-specific architectures › database accelerator
database machine
0.011987
A Relational Database System Architecture Based on a Vector Processing Method · ICDE 1987

Methods — techniques the papers use, named apart from their topics

parametric model checking · 0.0EFSM · 0.0vectorization · 0.0pipelined vector processing · 0.0
YearPublicationVenuePosition
2004 A Flexible and High-Reliable HW/SW Co-Design Method for Real-Time Embedded Systems
abstract
In this paper, we propose a flexible and high-reliable HW/SW co-design method for real-time systems consisting of multiple functional modules using general purpose components such as DSP, CPU and memory. In our method, we specify a system as a parallel composition of concurrent periodic EFSMs with timing constraints. As communication primitives among EFSMs, multi-way synchronization mechanism can be specified. Here, we propose a technique for efficient development of real-time embedded systems considering both reliability and cost-performance. For the purpose, using a parametric model checking technique, we derive a parameter condition which must hold for the system to proceed without deadlocks and satisfy given timing constraints. Based on the derived parameter condition and cost-performance characteristic of available components, an appropriate combination of components is automatically selected so that the total cost is minimized. We have developed a design support tool based on the proposed technique. By applying our method to development of a basic functionality of a cellular phone, we could decide which functional modules should be implemented as dedicated HW units or on-chip-CPUs' software, and select suitable DSPs and memories with low costs.
Tomoya Kitani, Yoshifumi Takamoto, Keiichi Yasumoto, Akio Nakata, Teruo Higashino
RTSS2
2003 Design and Implementation of Priority Queuing Mechanism on FPGA Using Concurrent Periodic EFSMs and Parametric Model Checking
Tomoya Kitani, Yoshifumi Takamoto, Isao Naka, Keiichi Yasumoto, Akio Nakata, Teruo Higashino
FPL2
2002 Design and Implementation of FPGA Circuits for High Speed Network Monitors
Masayuki Kirimura, Yoshifumi Takamoto, Takanori Mori, Keiichi Yasumoto, Akio Nakata, Teruo Higashino
FPL2
2000 A Scalable, Cost-Effective, and Flexible Disk System Using High-Performance Embedded-Processors
abstract
As a scalable, cost-effective, and flexible solution for data-intensive systems, we are exploring active-network-storage (ANS), which is an array of ANS disk drives. The ANS drive improves flexibility by using a modular software design; that is, users can specify functions of the ANS drive by loading/unloading the corresponding modules on it. To keep the ANS drive cost-effective, users are allowed to choose whether native code modules or platform-independent Java-bytecode modules are executed on the drive. We forecast that a current high-performance embedded-processor is powerful enough to enable this modular design to be implemented and to provide a scalable, cost-effective, and flexible ANS system. We have confirmed our forecast by conducting an experiment with an ANS drive prototype with a 200 MHz embedded-processor running database sequential scanning and NFS, which are typical off-loaded functions with different characteristics. To evaluate scalability and cost-effectiveness of the ANS system, we estimated the throughput from measurements on our ANS prototype, and we compared it with the throughput that was measured on a 450 MHz Pentium II Xeon server. Our estimation indicates that the scan throughput of the ANS system increases up to 71 MB/s while that of the server saturates at 25 MB/s because of its CPU bottleneck. The NFS read/write throughputs of two ANS drives surpassed the server maximum throughputs.
Aki W. Tomita, Yoshifumi Takamoto, Shigekazu Inohara, Frederico B. Maciel, Hiroaki Odawara, Mamoru Sugie
ICPP3
1989 A relational database system architecture based on a vector-processing method
Shun'ichi Torii, Keiji Kojima, Seiichi Yoshizumi, Akiharu Sakata, Yoshifumi Takamoto, Shun Kawabe, Masami Takahashi
Inf. Sci.5
1987 A Relational Database System Architecture Based on a Vector Processing Method
abstract
A new relational database system architecture based on a vector processing method is presented. The similarity between table and vector structures was studied. This similarity implies that vector processors have high potential for the improvement of Relational Data Base Management System (RDBMS) performance. In commercial RDBMSs, however, data records are internally organized in complex pointer structures, to which vector processing is not directly applicable. We propose a new vectorization method by which data in the pointer structures are dynamically rearranged into vector form, and collectively processed using a pipelined vector processor. A new pipelined vector processor called an Integrated Database Processor (IDP) which is particularly suitable for our vectorization strategy was developed. IDP is designed as an optional hardware for a general purpose computer. The vectorization method and IDP are applied to Hitachi's new, recently-announced, commercial RDBMS (called RDB1/IDP). In this paper, the vectorization method and the architecture of IDP are described. The performance improvement is also described and analyzed.
Shun'ichi Torii, Keiji Kojima, Seiichi Yoshizumi, Akiharu Sakata, Yoshifumi Takamoto, Shun Kawabe, Masami Takahashi, Tsuguo Ishizuka
ICDE5