A high-level synthesis strategy is proposed for design of semiconcurrently self-checking devices. Attention is mainly focused on data path design. After identifying the reference architecture against which cost and performance are evaluated, a simultaneous scheduling-and-allocation strategy is presented for linear-code data flow graphs, allowing resource sharing between nominal and checking data paths. The proposed strategy is actually independent from a specific scheduling-and-allocation algorithm since it is essentially concerned with the introduction of the fault tolerance issue at high-abstraction level in any design environment. Conventional duplication with comparison, even if considered in a high-level synthesis strategy, leads to high circuit complexity increase. The proposed approach provides that the required checking periodicity is satisfied while minimizing additional functional units by means of maximum reuse of the resources available for the nominal computation as long as error detection ability is preserved. The strategy is then extended to deal with branches and loops in the data path. Risk of error aliasing due to resource sharing is analyzed.

A high-level synthesis approach is proposed for the design of semi-concurrently self-checking devices; attention is focused on data path design. After identifying the reference architecture against which cost and performances should be evaluated, a simultaneous scheduling-and-allocation algorithm is presented, allowing resource sharing between nominal and checking data paths. The algorithm grants that the required checking periodicity is satisfied while minimizing additional costs in terms of functional units. Risk of error aliasing due to resource sharing is analysed.

A methodology for the design of modular and optimized architectural blocks for the generation of local windows of pixels is presented. The proposed formalization and the related techniques follow a design approach derived from the window-based algorithmic decomposition of low- and medium-level image processing algorithms.>

Window-based parallel architectures are considered as target structures for the computation of low and medium level image processing algorithms. Their definition stems from a general reformulation of algorithms, based on local data processing. A methodology for high level global evaluation of such architectures is presented, considering the reachable performances of the structures as main significant parameters.>

A new reconfiguration algorithm for defect and fault tolerance in fast Fourier transform (FFT) two-dimensional arrays is presented. The reconfiguration scheme is based on the data flow of the algorithm to minimize the overhead due to the re-routing of information in the reconfigured array. Evaluation of the effectiveness of this approach shows a significant increase in system robustness with respect to other, non-dedicated reconfiguration approaches. Moreover, the possibility of choosing between two reconfiguration algorithms characterized by different complexities and efficiencies results in both an optimal, host-driven reconfiguration (particularly suited for end-of-production yield enhancement) and a fast, self-performed reconfiguration (suited for on-line reliability enhancement).>

Pipelined VLSI/WSI architectures supporting image coding transforms are defined and evaluated in the paper. The structures proposed in the paper have been derived by considering a common algorithmic kernel of the set of examined transforms. The possibility of reducing the computations to a common algorithmic version allows definition of flexible structures characterized by a “basic” pipeline - performing the common kernel of computation - and by transform-dependent input and output stages. Three different pipelines have been defined and figures of merit, such as silicon area occupation and throughput, have been evaluated for architectures comparisons.