Demo Data from SIGIR 2026 / reviewers in the wild / expert
Johannes Wikner
dblp:331/2554
· DBLP profile ↗
6ranked-venue papers
3as first author
6since 2021 · last 2025
—ORCID · conflict
Domains — the database's venue-derived domains; a paper can count in several
Security and privacy · 5 · 2 first-author · 5 since 2021Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Network and information security
5 papers |
Hardware security and side channels · 78% Systems and software security · 22% | |
| Computer architecture, parallel and distributed computing, and storage systems
4 papers |
Processor architecture and microarchitecture · 100% |
Topics — the 10 heaviest of 11, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware security and side channels › microarchitectural attacks
transient execution attack |
2.2 | 3 | 2025 | Breaking the Barrier: Post-Barrier Spectre Attacks · SP 2025 Inception: Exposing New Attack Surfaces with Training in Transient Execution · USENIX Security Symposium 2023 Phantom: Exploiting Decoder-detectable Mispredictions · MICRO 2023 |
Processor architecture and microarchitecture
speculative execution |
1.3 | 2 | 2023 | Inception: Exposing New Attack Surfaces with Training in Transient Execution · USENIX Security Symposium 2023 Phantom: Exploiting Decoder-detectable Mispredictions · MICRO 2023 |
Hardware security and side channels › hardware attacks
side-channel and fault attacks |
0.9 | 1 | 2025 | Branch Privilege Injection: Compromising Spectre v2 Hardware Mitigations by Exploiting Branch Predictor Race Conditions · USENIX Security Symposium 2025 |
Systems and software security › vulnerability analysis
attack surface discovery |
0.7 | 1 | 2023 | Inception: Exposing New Attack Surfaces with Training in Transient Execution · USENIX Security Symposium 2023 |
Hardware security and side channels
microarchitectural attacks |
0.7 | 1 | 2023 | Phantom: Exploiting Decoder-detectable Mispredictions · MICRO 2023 |
Processor architecture and microarchitecture › speculative execution
transient execution |
0.7 | 1 | 2023 | Inception: Exposing New Attack Surfaces with Training in Transient Execution · USENIX Security Symposium 2023 |
Systems and software security › exploitation
arbitrary code execution |
0.6 | 1 | 2022 | RETBLEED: Arbitrary Speculative Code Execution with Return Instructions · USENIX Security Symposium 2022 |
Hardware security and side channels › microarchitectural attacks › transient execution attack
speculative execution attack |
0.6 | 1 | 2022 | RETBLEED: Arbitrary Speculative Code Execution with Return Instructions · USENIX Security Symposium 2022 |
Operating systems › system security › operating system security
kernel security |
0.3 | 1 | 2025 | Breaking the Barrier: Post-Barrier Spectre Attacks · SP 2025 |
Processor architecture and microarchitecture
branch prediction |
0.3 | 1 | 2025 | Branch Privilege Injection: Compromising Spectre v2 Hardware Mitigations by Exploiting Branch Predictor Race Conditions · USENIX Security Symposium 2025 |
Methods — techniques the papers use, named apart from their topics
microcode analysis · 2.6IBPB analysis · 2.6fuzzing · 1.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Rubicon: Precise Microarchitectural Attacks with Page-Granular MassagingabstractMicroarchitectural attacks like Rowhammer and Spectre rely on precisely targeting specific memory page frames despite the inherent unpredictability of memory allocation. Due to the lack of a generic mechanism to accurately place the target data in the pages of interest, these attacks resort to spraying their target or scanning the entire physical memory for it. These approaches, however, suffer from unreliability and inefficiency. In contrast, the deterministic behavior of page allocators presents an opportunity to enhance existing attacks and enable new ones.This paper introduces Rubicon, a novel technique for page-granular physical memory massaging within the Linux kernel’s Zoned Buddy Allocator (ZBA). Rubicon leverages three new primitives that enable placing a page frame at the head of any chosen ZBA free list, ensuring it is prioritized for allocation regardless of its initial state or per-CPU freelist association. Using Rubicon, we build the first deterministic privilege escalation Rowhammer exploit on x86 with a success rate of 100%. Our integration of Rubicon into a recent Spectre attack shows that the root hash of /etc/shadow can now be leaked in 27.8 and 9.5 seconds on AMD and Intel systems — a 6.8× and 284× speedup over the original attack, respectively. We also propose and evaluate practical mitigations for Rubicon, which limit page movement between ZBA lists with negligible performance and fragmentation impact. Matej Bölcskei, Patrick Jattke, Johannes Wikner, Kaveh Razavi |
EuroS&P | 3 |
| 2025 | Breaking the Barrier: Post-Barrier Spectre AttacksabstractThe effectiveness of transient execution defenses rests on obscure model-specific operations that must be correctly implemented in microcode and applied by software. In this paper, we study branch predictor invalidation through Indirect Branch Predictor Barrier (IBPB) for x86 processors, which is a cornerstone defense against cross-context and cross-privilege Spectre attacks, and discover new vulnerabilities in both its microcode implementation and application by software. Concretely, we demonstrate two new post-barrier speculative return target hijacks on Intel and AMD CPUs. First, we show an end-to-end cross-process attack that leaks the hash of the root password from a suid process. This attack works despite IBPB on recent generations of Intel processors due to a microcode implementation flaw. Second, we show that an unprivileged attacker can leak privileged memory on AMD Zen 1(+)/2 processors despite the deployed IBPB mitigation, due to how IBPB is applied by the Linux kernel. We propose using a chicken bit to disable exploitable return predictions on affected Intel CPUs and a software patch for the Linux kernel to safely use IBPB on affected AMD CPUs. Johannes Wikner, Kaveh Razavi |
SP | 1 |
| 2025 | Branch Privilege Injection: Compromising Spectre v2 Hardware Mitigations by Exploiting Branch Predictor Race Conditions
Sandro Rüegge, Johannes Wikner, Kaveh Razavi |
USENIX Security Symposium | 2 |
| 2023 | Phantom: Exploiting Decoder-detectable MispredictionsabstractViolating the Von Neumann sequential processing principle at the microarchitectural level is commonplace to reach high performing CPU hardware — violations are safe as long as software executes correctly at the architectural interface. Speculative execution attacks exploit these violations and queue up secret-dependent memory accesses allowed by long speculation windows due to the late detection of these violations in the pipeline. In this paper, we show that recent AMD and Intel CPUs speculate very early in their pipeline, even before they decode the current instruction. This mechanism enables new sources of speculation to be triggered from almost any instruction, enabling a new class of attacks that we refer to as Phantom. Unlike Spectre, Phantom speculation windows are short since the violations are detected early. Nonetheless, Phantom allows for transient fetch and transient decode on all recent x86-based microarchitectures, and transient execution on AMD Zen 1 and 2. We build a number of exploits using these new Phantom primitives and discuss why mitigating them is difficult in practice. Johannes Wikner, Daniël Trujillo, Kaveh Razavi |
MICRO | 1 |
| 2023 | Inception: Exposing New Attack Surfaces with Training in Transient Execution
Daniël Trujillo, Johannes Wikner, Kaveh Razavi |
USENIX Security Symposium | 2 |
| 2022 | RETBLEED: Arbitrary Speculative Code Execution with Return Instructions
Johannes Wikner, Kaveh Razavi |
USENIX Security Symposium | 1 |