As FPGAs become ubiquitous compute platforms, existing research has focused on enabling virtualization features to facilitate fine-grained FPGA sharing. We employ an overlay architecture which enables arbitrary, independent user logic to share portions of a single FPGA by dividing the FPGA into independently reconfigurable slots. We then explore scheduling possibilities to effectively time- and space-multiplex the virtualized FPGA by introducing Nimblock. The Nimblock scheduling algorithm balances application priorities and performance degradation to improve response time and reduce deadline violations. Unlike other algorithms, Nimblock explores both preemption and pipelining as a scheduling parameter to dynamically change resource allocations, and automatically allocates resources to enable suitable parallelism for an application without additional user input. We demonstrate system feasibility by realizing the complete system on a Xilinx ZCU106 FPGA. We evaluate our algorithm and validate its efficacy by measuring results from real workloads running on the board with different real-time constraints and priority levels. In our exploration, we compare our novel Nimblock algorithm against a no-sharing and no-virtualization baseline algorithm and three other algorithms which support sharing and virtualization. We achieve up to 5x lower average response time when compared to the baseline algorithm and up to 2.1x average response time improvement over competitive scheduling algorithms that support sharing within our virtualization environment. We additionally demonstrate up to 49% fewer deadline violations and up to 2.6x lower tail response times when compared to other high-performance algorithms.

Solid State Drives (SSDs) have become increasingly popular due to their superior access latency and bandwidth compared to Hard Disk Drives (HDDs). However, to fully understand the impact of SSD design and microarchitecture on end-to-end application performance, researchers need to move beyond treating SSDs as black-box components. Unfortunately, purchasing multiple SSDs for research is expensive and ineffective since the underlying microarchitecture is still unknown to the system designer. While simulators have become the most popular method for studying SSDs, existing software-based simulators lack real data transfers and cannot simulate the latency from NVMe and PCIe interfaces. Additionally, simulating the entire SSD using software codes is time-consuming and limits the number of experiments that can be run in a reasonable amount of time. To address these issues, we present FSSD, an FPGA-based emulation system that models the latency and access patterns of an actual NVMe SSD. FSSD takes advantage of the flexibility of an FPGA, enabling users to customize SSD microarchitecture features and explore the design space for data-intensive applications. FSSD can be interacting with real operating systems, instead of relying on Virtual Machines like most other software simulators do. Evaluations show that FSSD provides over 1000x speedup compared to software-based simulation using the SimpleSSD simulator. The ability to customize SSD parameters and emulate NAND latency with high precision makes FSSD a valuable platform for SSD research and development. FSSD is also open-sourced to benefit the research community.

As FPGAs become ubiquitous compute platforms, existing research has focused on enabling virtualization features to facilitate finegrained FPGA sharing. We employ an overlay architecture which enables arbitrary, independent user logic to share portions of a single FPGA by dividing the FPGA into independently reconfigurable slots. We then explore scheduling possibilities to effectively time- and space-multiplex the virtualized FPGA by introducing Nimblock. The Nimblock scheduling algorithm balances application priorities and performance degradation to improve response time and reduce deadline violations. Unlike other algorithms, Nimblock explores preemption as a scheduling parameter to dynamically change resource allocations, and automatically allocates resources to enable suitable parallelism for an application without additional user input. In our exploration, we evaluate five scheduling algorithms: a baseline, three existing algorithms, and our novel Nimblock algorithm. We demonstrate system feasibility by realizing the complete system on a Xilinx ZCU106 FPGA and evaluating on a set of real-world benchmarks. In our results, we achieve up to 5.7× lower average response times when compared to a no-sharing and no-virtualization scheduling algorithm and up to 2.1× average response time improvement over competitive scheduling algorithms that support sharing within our virtualization environment. We additionally demonstrate up to 49% fewer deadline violations and up to 2.6× lower tail response times when compared to other high-performance algorithms.