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Zhilei Xu

dblp:34/2799 · DBLP profile ↗
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18ranked-venue papers
6as first author
9since 2021 · last 2026
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 6 · 5 first-author · 6 since 2021Software engineering, systems software and programming languages · 6 · 1 since 2021Systems, architecture and hardware · 3 · 1 first-author · 1 since 2021Computer networks · 1Security and privacy · 1Human-computer interaction and ubiquitous computing · 1 · 1 since 2021Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
4 papers
Hardware accelerators and domain-specific architectures · 51% High-performance computing · 17% Memory systems · 15%
Software engineering, system software, and programming languages
8 papers
Debugging and program repair · 33% Program analysis · 25% Operating systems · 14%
Network and information security
2 papers
Cryptographic protocols and secure computation · 64% Hardware security and side channels · 19% Malware analysis · 16%

Topics — the 19 heaviest of 23, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Cryptographic protocols and secure computation
secure multiparty computation
0.612022
PPMLAC: high performance chipset architecture for secure multi-party computation · ISCA 2022
Hardware accelerators and domain-specific architectures
cryptographic accelerator
0.612022
PPMLAC: high performance chipset architecture for secure multi-party computation · ISCA 2022
Debugging and program repair
record and replay
0.222010
Language-based replay via data flow cut · SIGSOFT FSE 2010
R2: An Application-Level Kernel for Record and Replay · OSDI 2008
High-performance computing
distributed memory systems
0.212014
MSL: A Synthesis Enabled Language for Distributed Implementations · SC 2014
Hardware security and side channels
side-channel resistance
0.212022
PPMLAC: high performance chipset architecture for secure multi-party computation · ISCA 2022
Malware analysis
rootkit detection
0.112012
Tracking Rootkit Footprints with a Practical Memory Analysis System · USENIX Security Symposium 2012
Program analysis › dynamic analysis
program tracing
0.112011
Data-driven synthesis for object-oriented frameworks · OOPSLA 2011
Program verification
model checking
0.112009
MODIST: Transparent Model Checking of Unmodified Distributed Systems · NSDI 2009
Distributed systems
fault tolerance
0.112009
MODIST: Transparent Model Checking of Unmodified Distributed Systems · NSDI 2009
Electronic design automation
model checking
0.112009
MODIST: Transparent Model Checking of Unmodified Distributed Systems · NSDI 2009
Debugging and program repair
fault localization
0.112008
R2: An Application-Level Kernel for Record and Replay · OSDI 2008
Operating systems › kernel
kernel design
0.112008
R2: An Application-Level Kernel for Record and Replay · OSDI 2008
Program analysis
static analysis
0.112008
Conditional correlation analysis for safe region-based memory management · PLDI 2008
Memory systems
memory management
0.112008
Conditional correlation analysis for safe region-based memory management · PLDI 2008
Memory systems › memory management
region-based memory management
0.112008
Conditional correlation analysis for safe region-based memory management · PLDI 2008
Requirements engineering and software design › software architecture › reusable architecture
object-oriented frameworks
0.012011
Data-driven synthesis for object-oriented frameworks · OOPSLA 2011
Program analysis
data flow analysis
0.012010
Language-based replay via data flow cut · SIGSOFT FSE 2010
Program analysis › error detection
dangling pointer detection
0.012008
Conditional correlation analysis for safe region-based memory management · PLDI 2008
Programming languages and type systems › type systems
type soundness
0.012008
Conditional correlation analysis for safe region-based memory management · PLDI 2008

Methods — techniques the papers use, named apart from their topics

FPGA prototyping · 1.1software synthesis · 0.4generative programming · 0.4conditional correlation analysis · 0.2abstraction-based indexing · 0.1data flow cut · 0.1record and replay · 0.1kernel instrumentation · 0.1hang analysis · 0.1
YearPublicationVenuePosition
2026 A multi-channel adaptive neural network for querying the optimal time-varying damage route with collective spatial keywords
Zhilei Xu, Wei Huang 0008
Eng. Appl. Artif. Intell.1
2026 A delay-Adaptive neural network for querying TOP-k critical vertices on time-Dependent shortest paths
Zhilei Xu, Wei Huang 0008, Jiaqian Bi
Neural Networks1
2024 Hybrid Ensemble Polynomial Neural Network Classifier: Analysis and Design
abstract
In this paper, we propose a hybrid ensemble polynomial neural network (HEPNN) with the aid of polynomial neural network (PNN) and hybrid ensemble polynomials neurons (HEPNs). Two types of HEPNs including ensemble radial-based-function polynomial neuron (ERPN) and ensemble polynomial neuron (EPN) are proposed. ERPN and EPN are generalized polynomial neurons based on ensemble architecture. To address the problem of multiple covariance in traditional PNN neural networks, correlation coefficients and performance are utilized to select neurons replacing the original selection of nodes by performance only. The main strategies of HEPNN design are as follows: First, the first layer of the network consists of ERPN that are utilized to reflect the structure encountered between the data, while the second and higher layers consists of EPN, which reflect higher polynomial-order relationships between input and output data. Second, particle swarm optimization (PSO) is adopted to optimize the architecture of HEPNN. A comparative study shows the proposed HEPNN has better performance than other state-of-art models reported in literature.
Wei Huang 0008, Zhilei Xu, Sung-Kwun Oh
CSCWD3
2024 Temporal Sequential Wave Neural Network for Solving the Optimal Cognitive Subgraph Query Problem
Jiaqian Bi, Zhilei Xu
ICIC (3)2
2024 An adaptive time-varying neural network for solving K optimal time-varying destroy locations query problem
Zhilei Xu, Wei Huang 0008
Knowl. Based Syst.1
2022 PPMLAC: high performance chipset architecture for secure multi-party computation
abstract
Privacy issue is a main concern restricting data sharing and cross-organization collaborations. While Privacy-Preserving Machine Learning techniques such as Multi-Party Computations (MPC), Homomorphic Encryption, and Federated Learning are proposed to solve this problem, no solution exists with both strong security and high performance to run large-scale, complex machine learning models. This paper presents PPMLAC, a novel chipset architecture to accelerate MPC, which combines MPC's strong security and hardware's high performance, eliminates the communication bottleneck from MPC, and achieves several orders of magnitudes speed up over software-based MPC. It is carefully designed to only rely on a minimum set of simple hardware components in the trusted domain, thus is robust against side-channel attacks and malicious adversaries. Our FPGA prototype can run mainstream large-scale ML models like ResNet in near real-time under a practical network environment with non-negligible latency, which is impossible for existing MPC solutions.
Zhilei Xu, Mingyu Gao 0001
ISCA2
2022 A wave time-varying neural network for solving the time-varying shortest path problem
Zhilei Xu, Wei Huang 0008
Appl. Intell.1
2022 The minimum regret path problem on stochastic fuzzy time-varying networks
Wei Huang 0008, Zhilei Xu, Liehuang Zhu
Neural Networks2
2021 A time-varying neural network for solving minimum spanning tree problem on time-varying network
Zhilei Xu, Wei Huang 0008
Neurocomputing1
2014 MSL: A Synthesis Enabled Language for Distributed Implementations
abstract
This paper demonstrates how ideas from generative programming and software synthesis can help support the development of bulk-synchronous distributed memory kernels. These ideas are realized in a new language called MSL, a C-like language that combines synthesis features with high level notations for array manipulation and bulk-synchronous parallelism to simplify the semantic analysis required for synthesis. The paper shows that by leveraging these high level notations, it is possible to scale the synthesis and automated bug-finding technologies that underlie MSL to realistic computational kernels. Specifically, we demonstrate the methodology through case studies implementing non-trivial distributed kernels -- both regular and irregular -- from the NAS parallel benchmarks. We show that our approach can automatically infer many challenging details from these benchmarks and can enable high level implementation ideas to be reused between similar kernels. We also demonstrate that these high level notations map easily to low level C code and show that the performance of this generated code matches that of handwritten Fortran.
Zhilei Xu, Shoaib Kamil 0001, Armando Solar-Lezama
SC1
2014 Modular Synthesis of Sketches Using Models
Rohit Singh 0002, Rishabh Singh, Zhilei Xu, Rebecca Krosnick, Armando Solar-Lezama
VMCAI3
2012 Tracking Rootkit Footprints with a Practical Memory Analysis System
Weidong Cui, Marcus Peinado, Zhilei Xu, Ellick Chan
USENIX Security Symposium3
2011 Data-driven synthesis for object-oriented frameworks
abstract
Software construction today often involves the use of large frameworks. The challenge in this type of programming is that object-oriented frameworks tend to grow exceedingly intricate; they spread functionality among numerous classes, and any use of the framework requires knowledge of many interacting components. We present a system named MATCHMAKER that from a simple query synthesizes code that interacts with the framework. The query consists of names of two framework classes, and our system produces code enabling interaction between them. MATCHMAKER relies on a database of dynamic program traces called DELIGHT that uses novel abstraction-based indexing techniques to answer queries about the evolution of heap connectivity in a matter of seconds.
Kuat Yessenov, Zhilei Xu, Armando Solar-Lezama
OOPSLA2
2010 Language-based replay via data flow cut
abstract
A replay tool aiming to reproduce a program's execution interposes itself at an appropriate replay interface between the program and the environment. During recording, it logs all non-deterministic side effects passing through the interface from the environment and feeds them back during replay. The replay interface is critical for correctness and recording overhead of replay tools.
Ming Wu 0007, Fan Long, Xi Wang 0005, Zhilei Xu, Haoxiang Lin, Xuezheng Liu, Huayang Guo, Lidong Zhou, Zheng Zhang 0001
SIGSOFT FSE4
2009 MODIST: Transparent Model Checking of Unmodified Distributed Systems
Tisheng Chen, Ming Wu 0007, Zhilei Xu, Xuezheng Liu, Haoxiang Lin, Mao Yang 0004, Fan Long, Lidong Zhou
NSDI4
2008 Hang analysis: fighting responsiveness bugs
abstract
Soft hang is an action that was expected to respond instantly but instead drives an application into a coma. While the application usually responds eventually, users cannot issue other requests while waiting. Such hang problems are widespread in productivity tools such as desktop applications; similar issues arise in server programs as well. Hang problems arise because the software contains blocking or time-consuming operations in graphical user interface (GUI) and other time-critical call paths that should not.
Xi Wang 0005, Xuezheng Liu, Zhilei Xu, Haoxiang Lin, Xiaoge Wang, Zheng Zhang 0001
EuroSys4
2008 R2: An Application-Level Kernel for Record and Replay
Xi Wang 0005, Xuezheng Liu, Zhilei Xu, Ming Wu 0007, M. Frans Kaashoek, Zheng Zhang 0001
OSDI5
2008 Conditional correlation analysis for safe region-based memory management
abstract
Region-based memory management is a popular scheme in systems software for better organization and performance. In the scheme, a developer constructs a hierarchy of regions of different lifetimes and allocates objects in regions. When the developer deletes a region, the runtime will recursively delete all its subregions and simultaneously reclaim objects in the regions. The developer must construct a consistent placement of objects in regions; otherwise, if a region that contains pointers to other regions is not always deleted before pointees, an inconsistency will surface and cause dangling pointers, which may lead to either crashes or leaks.
Xi Wang 0005, Zhilei Xu, Xuezheng Liu, Xiaoge Wang, Zheng Zhang 0001
PLDI2