Demo Data from SIGIR 2026 / reviewers in the wild / expert
Adamantini Peratikou
dblp:34/8823
· DBLP profile ↗
5ranked-venue papers
1as first author
4since 2021 · last 2025
0000-0003-1273-8910ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Security and privacy · 4 · 1 first-author · 4 since 2021Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Interconnection networks and networks-on-chip · 67% Electronic design automation · 17% Hardware reliability and fault tolerance · 17% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Interconnection networks and networks-on-chip › routing algorithms
adaptive routing |
0.3 | 1 | 2017 | Routing and Fault Tolerance in Z-Fat Tree · IEEE Trans. Parallel Distributed Syst. 2017 |
Interconnection networks and networks-on-chip › network topology › tree networks
fat-tree network |
0.3 | 1 | 2017 | Routing and Fault Tolerance in Z-Fat Tree · IEEE Trans. Parallel Distributed Syst. 2017 |
Interconnection networks and networks-on-chip › network reliability
link fault tolerance |
0.3 | 1 | 2017 | Routing and Fault Tolerance in Z-Fat Tree · IEEE Trans. Parallel Distributed Syst. 2017 |
Hardware reliability and fault tolerance
network fault tolerance |
0.3 | 1 | 2017 | Routing and Fault Tolerance in Z-Fat Tree · IEEE Trans. Parallel Distributed Syst. 2017 |
Interconnection networks and networks-on-chip › network topology
network topology design |
0.3 | 1 | 2017 | Routing and Fault Tolerance in Z-Fat Tree · IEEE Trans. Parallel Distributed Syst. 2017 |
Electronic design automation › physical design
routing |
0.3 | 1 | 2017 | Routing and Fault Tolerance in Z-Fat Tree · IEEE Trans. Parallel Distributed Syst. 2017 |
Methods — techniques the papers use, named apart from their topics
round-robin routing · 0.3fault tolerance algorithm · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Reducing SOC Analysts Alert Fatigue via Real-Time CTI Correlation and Deduplication
Sotiris Koumourou, Adamantini Peratikou, Eliana Stavrou, Savvas Theodoulou, Stavros Stavrou |
CRITIS | 2 |
| 2025 | CY-TRUST: A Sectorial SOC Framework for Enhanced National and Cross-Border Cybersecurity Resilience
Adamantini Peratikou, Evagoras Charalambous, Eliana Stavrou, Panayiota Smyrli, George Hadjichristophi, Stavros Stavrou |
CRITIS | 1 |
| 2025 | A Multi-dimensional Cyber Range-Powered Scoring Framework for Evaluating Cyber Resilience of Critical Infrastructures
Savvas Theodoulou, Eliana Stavrou, Adamantini Peratikou, Stavros Stavrou |
CRITIS | 3 |
| 2023 | A novel Evil Twin MiTM attack through 802.11v protocol exploitation
Constantinos Louca, Adamantini Peratikou, Stavros Stavrou |
Comput. Secur. | 2 |
| 2017 | Routing and Fault Tolerance in Z-Fat TreeabstractFat tree topologies have been extensively used as interconnection networks for high performance computing, cluster and data center systems, with their most recent variants able to fairly extend and scale to accommodate higher processing power. While each progressive and evolved fat-tree topology includes some extra advancements, these networks do not fully address all the issues of large scale HPC. We propose a topology called Zoned-Fat tree (Z-Fat tree,) which is a further extension to the fat trees. The extension relates to the provision of extra degree of connectivity to utilize the extra ports per switches (routing nodes), that are, in some cases, not utilized by the architectural constraints of other variants of fat trees, and hence increases the bisection bandwidth, reduces the latency and supplies additional paths for fault tolerance. To support and profit from the extra links, we propose an adaptive low latency routing for up traffic which is based on a series of leading direction bits predefined at the source; furthermore we suggest a deterministic routing by implementing a dynamic round robin algorithm that overtakes D-mod-K in same cases and guarantees the utilization of all the extra links. We also propose a fault tolerance algorithm, named recoil-and-reroute which makes use of the extra links to ensure higher message delivery even in the presence of faulty links and switches. Mo Adda, Adamantini Peratikou |
IEEE Trans. Parallel Distributed Syst. | 2 |