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Chunao Liu

dblp:349/5061 · DBLP profile ↗
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2ranked-venue papers
0as first author
2since 2021 · last 2025
0009-0004-1448-8403ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 since 2021Software engineering, systems software and programming languages · 2 · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Cloud and datacenter computing · 45% Processor architecture and microarchitecture · 37% Parallel and multicore computing · 15%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture
multicore design
1.522025
HardHarvest: Hardware-Supported Core Harvesting for Microservices · ISCA 2025
μManycore: A Cloud-Native CPU for Tail at Scale · ISCA 2023
Cloud and datacenter computing
microservices
0.922025
μManycore: A Cloud-Native CPU for Tail at Scale · ISCA 2023
HardHarvest: Hardware-Supported Core Harvesting for Microservices · ISCA 2025
Cloud and datacenter computing › quality of service
tail latency
0.922025
μManycore: A Cloud-Native CPU for Tail at Scale · ISCA 2023
HardHarvest: Hardware-Supported Core Harvesting for Microservices · ISCA 2025
Parallel and multicore computing
processor allocation
0.912025
HardHarvest: Hardware-Supported Core Harvesting for Microservices · ISCA 2025
Cloud and datacenter computing
serverless computing
0.912025
HardHarvest: Hardware-Supported Core Harvesting for Microservices · ISCA 2025
Processor architecture and microarchitecture
many-core architecture
0.712023
μManycore: A Cloud-Native CPU for Tail at Scale · ISCA 2023
Memory systems
cache coherence
0.212023
μManycore: A Cloud-Native CPU for Tail at Scale · ISCA 2023

Methods — techniques the papers use, named apart from their topics

hardware request scheduling · 0.9TLB/cache partitioning · 0.9
YearPublicationVenuePosition
2025 HardHarvest: Hardware-Supported Core Harvesting for Microservices
abstract
In microservice environments, users size their virtual machines (VMs) for peak loads, leaving cores idle much of the time.To improve core utilization and overall throughput, it is instructive to consider a recently-introduced software technique for environments with relatively long-running monolithic applications: Core Harvesting.With this technique, Harvest VMs running batch applications temporarily steal idle cores allocated by Primary VMs running latency-critical applications, and return them on demand.Unfortunately, re-assigning cores across VMs has substantial overhead, resulting from hypervisor calls, context switching, and flushing TLBs/caches.While such overhead is acceptable in monolithic application environments, it would be prohibitive in environments with sub-millisecond microservices.To address this problem, this paper proposes, for the first time, an architecture for core harvesting in hardware.The architecture, called HardHarvest, targets microservices.It aims to: 1) maximize core utilization, 2) minimize impact on Primary VM tail latency, and 3) boost Harvest VM throughput.HardHarvest eliminates software overheads by using in-hardware request scheduling and partitioning TLBs/caches with a smart replacement algorithm.On average, compared to state-of-the-art software core harvesting, HardHarvest increases core utilization by 1.5×, increases Harvest VM throughput by 1.8×, and reduces Primary VM tail latency by 6.0×.
Jovan Stojkovic, Chunao Liu, Muhammad Shahbaz 0001, Josep Torrellas
ISCA2
2023 μManycore: A Cloud-Native CPU for Tail at Scale
abstract
Microservices are emerging as a popular cloud-computing paradigm. Microservice environments execute typically-short service requests that interact with one another via remote procedure calls (often across machines), and are subject to stringent tail-latency constraints. In contrast, current processors are designed for traditional monolithic applications. They support global hardware cache coherence, provide large caches, incorporate microarchitecture for long-running, predictable applications (such as advanced prefetching), and are optimized to minimize average latency rather than tail latency.
Jovan Stojkovic, Chunao Liu, Muhammad Shahbaz 0001, Josep Torrellas
ISCA2