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Kwanseok Choi

dblp:349/5062 · DBLP profile ↗
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3ranked-venue papers
0as first author
3since 2021 · last 2024
0009-0000-1570-4463ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Hardware accelerators and domain-specific architectures · 59% Memory systems · 41%
Computer graphics and multimedia
1 paper
Rendering · 100%
Artificial intelligence
2 papers
Efficient and distributed learning · 54% 3D vision · 46%

Topics — the 8 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures
machine learning accelerator
0.812024
MoNDE: Mixture of Near-Data Experts for Large-Scale Sparse Models · DAC 2024
Hardware accelerators and domain-specific architectures › machine learning accelerator › DNN inference
mixture-of-experts inference
0.812024
MoNDE: Mixture of Near-Data Experts for Large-Scale Sparse Models · DAC 2024
Memory systems › processing-in-memory
near-data processing
0.812024
MoNDE: Mixture of Near-Data Experts for Large-Scale Sparse Models · DAC 2024
Memory systems
processing-in-memory
0.812024
MoNDE: Mixture of Near-Data Experts for Large-Scale Sparse Models · DAC 2024
Rendering
neural rendering
0.712023
NeuRex: A Case for Neural Rendering Acceleration · ISCA 2023
Hardware accelerators and domain-specific architectures
neural rendering accelerator
0.712023
NeuRex: A Case for Neural Rendering Acceleration · ISCA 2023
Machine learning › Efficient and distributed learning
model offloading
0.212024
MoNDE: Mixture of Near-Data Experts for Large-Scale Sparse Models · DAC 2024
Computer vision › 3D vision › 3d scene modeling › scene representation
neural scene representation
0.212023
NeuRex: A Case for Neural Rendering Acceleration · ISCA 2023

Methods — techniques the papers use, named apart from their topics

multi-resolution hash encoding · 2.0near-data computing · 1.5expert offloading · 1.5
YearPublicationVenuePosition
2024 MoNDE: Mixture of Near-Data Experts for Large-Scale Sparse Models
abstract
Mixture-of-Experts (MoE) large language models (LLM) have memory requirements that often exceed the GPU memory capacity, requiring costly parameter movement from secondary memories to the GPU for expert computation. In this work, we present Mixture of Near-Data Experts (MoNDE), a near-data computing solution that efficiently enables MoE LLM inference. MoNDE reduces the volume of MoE parameter movement by transferring only the hot experts to the GPU, while computing the remaining cold experts inside the host memory device. By replacing the transfers of massive expert parameters with the ones of small activations, MoNDE enables far more communication-efficient MoE inference, thereby resulting in substantial speedups over the existing parameter of-floading frameworks for both encoder and decoder operations.
Kwanseok Choi, Youngmock Cho, Jaehoon Cho, Jaewoong Sim
DAC2
2023 SDM: Sharing-Enabled Disaggregated Memory System with Cache Coherent Compute Express Link
abstract
Disaggregated memory has been gaining significant traction as a promising solution for scaling memory capacity and better utilizing memory resources in data centers. However, a disaggregated memory system that can simultaneously achieve high performance and user transparency is still not available. Although some modern interconnect technologies now feature hardware coherence protocols that can potentially enable data sharing among multiple computing nodes in a user-transparent manner, naively applying these technologies to disaggregated memory systems results in non-negligible performance overheads. In this work, we propose SDM, a sharing-enabled, cache-coherent disaggregated memory system that effectively utilizes modern interconnect technology. The key design principle of SDM is to implement a novel, dedicated control flow that efficiently enables data sharing among multiple computing nodes without the need to modify user applications, by leveraging the message types defined in the modern memory expansion standard, Compute Express Link (CXL). We also introduce resource management and speculative memory access mechanisms that do not interfere with normal memory transaction channels, thereby further improving the performance of disaggregated memory systems. We evaluate our design based on an in-house simulation framework with detailed analytical models that mimic a cache-coherent multi-node disaggregated memory system. The results show that SDM outperforms the optimized baseline system, which is similar to the one employing CXL 3.0, by$5.77\times$and$2.65\times$for two distinctive benchmark suites.
Hyokeun Lee, Kwanseok Choi, Jaewoong Sim
PACT2
2023 NeuRex: A Case for Neural Rendering Acceleration
abstract
This paper presents NeuRex, an accelerator architecture that efficiently performs the modern neural rendering pipeline with an algorithmic enhancement and supporting hardware. NeuRex leverages the insights from an in-depth analysis of the state-of-the-art neural scene representation to make the multi-resolution hash encoding, which is the key operational primitive in modern neural renderings, more hardware-friendly and features a specialized hash encoding engine that enables us to effectively perform the primitive and the overall rendering pipeline. We implement and synthesize NeuRex using a commercial 28nm process technology and evaluate two versions of NeuRex (NeuRex-Edge, NeuRex-Server) on a range of scenes with different image resolutions for mobile and high-end computing platforms. Our evaluation shows that NeuRex achieves up to 9.88× and 3.11× speedups against the mobile and high-end consumer GPUs with a substantially small area overhead and lower energy consumption.
Kwanseok Choi, Joonho Whangbo, Jaewoong Sim
ISCA2