This paper proposes a novel and efficient model for the estimation of post-FEC BER for high-speed serial links using FEC codes such as RS (544, 514) in the presence of DFE error propagation. The model employs the Markov model for DFE error propagation and incorporates concepts from the Gilbert-Elliott model. Using various optimization techniques, including Markov state aggregation, burst tables, and adaptive neglect of rare cases, it achieves a computation time that is only 1.658% of that required by previous work for the post-FEC BER computation with RS (544, 514) FEC code and a 2-tap DFE. Furthermore, analyses demonstrate that its computation time increases less rapidly with respect to the number of DFE taps compared to previous works, indicating its better applicability for systems with more DFE taps or larger state spaces. Data measured from an FPGA-based behavior simulator proved that the model can accurately estimate post-FEC BER.

We have recently seen tremendous progress in realistic text-to-motion generation. Yet, the existing methods of-ten fail or produce implausible motions with unseen text inputs, which limits the applications. In this paper, we present OMG, a novel framework, which enables compelling motion generation from zero-shot open-vocabulary text prompts. Our key idea is to carefully tailor the pretrain-then-finetune paradigm into the text-to-motion generation. At the pre-training stage, our model improves the gener-ation ability by learning the rich out-of-domain inherent motion traits. To this end, we scale up a large unconditional diffusion model up to 1B parameters, so as to utilize the massive unlabeled motion data up to over 20M motion instances. At the subsequent fine-tuning stage, we intro-duce motion ControlNet, which incorporates text prompts as conditioning information, through a trainable copy of the pre-trained model and the proposed novel Mixture-of-Controllers (MoC) block. MoC block adaptively rec-ognizes various ranges of the sub-motions with a cross-attention mechanism and processes them separately with the text-token-specific experts. Such a design effectively aligns the CLIP token embeddings of text prompts to var-ious ranges of compact and expressive motion features. Ex-tensive experiments demonstrate that our OMG achieves significant improvements over the state-of-the-art meth-ods on zero-shot text-to-motion generation. Project page: https://tr3e.github.io/omg-page.

With the increasing speed and more stringent Bit Error Rate (BER) requirements of serial wireline links, FPGA-based SerDes (serializer/deserializer) simulation systems have gained widespread usage. As a fundamental component for BER simulation, there is a growing demand for Gaussian random number (GRN) generators that offer enhanced statistical accuracy, improved efficiency, and greater scalability. In this paper, we introduce a novel design methodology for GRN generators tailored for SerDes simulation systems. Unlike conventional approaches, this methodology treats GRNs as discrete values, is optimizable for specific GRN variances, supports pre-determined output ranges, and offers complete reconfigurability with respect to variance. A theoretical output range of$\pm 14\sigma$is exemplified. Synthesis results and statistical tests demonstrated that generators designed using the proposed method are statistically accurate while consuming low resources and providing complete reconfigurability.

In this article, a configurable and highly flexible four-level pulse amplitude modulation (PAM4) serializer/deserializer (SerDes) simulation system based on a field-programmable gate array (FPGA) is designed, which can simulate all bit rates currently supported by actual chips, such as 112 Gb/s. Compared to software simulation systems, the efficiency of this hardware simulation system is greatly improved. This simulation system allows parameterized configuration, and when paired with a CPU, it can save simulation data from various stages. Therefore, this simulation system can help integrated circuit (IC) designers save time and resources, design SerDes chips under different channel conditions, explore the error model of SerDes chips, and design improved equalization and forward error correction (FEC) schemes. Because some existing SerDes module algorithms are not publicly accessible, the commonly used SerDes module algorithms are summarized in this article, and some of them are modified. First, a parallel architecture for a scrambler/descrambler is designed using the Chisel language, which can be used to construct synchronous or asynchronous scramblers/descramblers of any parallel stage. Second, for the designed simulation system, the sign-to-sign Mueller–Muller phase detector (MMPD) from nonreturn-to-zero (NRZ) to PAM4 is introduced, eliminating the detection of rising or falling edges and instead performing phase detection between any two unit intervals (UIs). Experiments on the designed simulation system show a maximum signal-to-noise ratio (SNR) error of 0.05151 dB compared to theoretical results under the same bit error rate (BER) condition and a mean error of 0.03488 dB. The simulation results agree with the theoretical prediction.