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Hongki Sung

dblp:35/2693 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 1992
—ORCID · unresolved

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 61% Distributed systems · 30% Parallel and multicore computing · 9%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
cache coherence		 0.011992
A new compiler-directed cache coherence scheme for shared memory multiprocessors with fast and parallel explicit invalidation · ISCA 1992
Distributed systems
cache invalidation		 0.011992
A new compiler-directed cache coherence scheme for shared memory multiprocessors with fast and parallel explicit invalidation · ISCA 1992
Memory systems › cache coherence › software cache coherence
compiler-directed cache coherence		 0.011992
A new compiler-directed cache coherence scheme for shared memory multiprocessors with fast and parallel explicit invalidation · ISCA 1992
Parallel and multicore computing › multiprocessor system
shared-memory multiprocessor		 0.011992
A new compiler-directed cache coherence scheme for shared memory multiprocessors with fast and parallel explicit invalidation · ISCA 1992
YearPublicationVenuePosition
1992 A Compiler Directed Cache Coherence Scheme with Fast and Parallel Explicit Invalidation
Ahmed Louri, Hongki Sung
 ICPP (1)2
1992 A new compiler-directed cache coherence scheme for shared memory multiprocessors with fast and parallel explicit invalidation
abstract
We propose a novel compiler-directed cache management scheme which allows parallel invalidation of a subset of array elements. The scheme limits non-stale data invalidations using a novel memory allocation technique. Its correctness is proved using a flow graph model. It is also shown that the scheme provides more cacheability than the previous compiler-directed ones and has lower overhead in determining read hit at runtime. A new performance parameter called unwanted invalidation ratio, for compiler-directed coherence schemes is also proposed.
Ahmed Louri, Hongki Sung
 ISCA2