A special multistack structure and optimization technique to partition, place, and wire the data-path macros in the form of the multistack structure are described, taking into account the connectivity of all the chip logic (data path, control logic, chip drivers, on-chip memory). The overall objective is: to fit the circuits within the chip boundary; to ensure data-path internal wirability; as well as external stack wirability to the other circuits; and to minimize wire lengths for wirability and timing. A tool for automatic multistack optimization has been implemented and applied successfully to layout high-density data path chips.>

As data-path chips such as microprocessors and RISC chips become more complex, multiple stacks of data-path macros are required to implement the entire data-path. The physical decomposition of a chip into a single data-path stack, and control logic of random logic as in the past is not always feasible. This paper describes a special multi-stack structure, optimization techniques and algorithms to partition, place and wire the data-path macros in the form of the multi-stack structure, taking into account the connectivity of the entire chip logic (data-path, control logic, chip drivers, on-chip memory). The overall objective is: (1) to fit the circuits within the chip, (2) to ensure data-path wireability, including stack to random logic wireability, and (3) to minimize wire lengths for wireability and timing. A tool for automatic multi-stack optimization has been implemented and applied successfully to layout some high density data-path chips.

A method is presented for floorplanning data-path chips by a technique of multi-terrain partitioning with integrated global wiring to partition the objects into terrains, followed by multistack placement and standard-cell placement. Requirements on terrain size, terrain shape, wirability, and timing are considered. Results obtained for some chip designs are presented.>