Bertrand Serlet

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4ranked-venue papers

1as first author

0since 2021 · last 1988

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems

4 papers

Electronic design automation · 84% Integrated circuit design · 16%

Topics — the 4 heaviest of 5, each with the papers that count most for it

Topic	Papers	Last	Evidence papers
Electronic design automation physical design	2	1988	A Structural Representation for VLSI Design · DAC 1988 Patchwork: Layout from Schematic Annotations · DAC 1988
Electronic design automation › logic synthesis boolean function realization	1	1987	Fast, Small, and Static Combinatorial CMOS Circuits · DAC 1987
Integrated circuit design digital circuit design	1	1987	Fast, Small, and Static Combinatorial CMOS Circuits · DAC 1987
Electronic design automation logic synthesis	1	1987	Fast, Small, and Static Combinatorial CMOS Circuits · DAC 1987

Methods — techniques the papers use, named apart from their topics

tree-structured boolean representation · 0.0cascode-switch style · 0.0

Year	Publication	Venue	Position
1988	Patchwork: Layout from Schematic Annotations Richard Barth, Louis Monier, Bertrand Serlet	DAC	3
1988	A Structural Representation for VLSI Design Richard Barth, Bertrand Serlet	DAC	2
1988	Parameterized Schematics Richard Barth, Bertrand Serlet, Pradeep S. Sindhu	DAC	2
1987	Fast, Small, and Static Combinatorial CMOS Circuits abstract We present ALPS, a new way to generate layout from boolean equations. We use an original tree-structured representation of arbitrary boolean expressions, more compact than classic disjunctive form, allowing fast symbolic manipulation and natural mapping onto silicon. This implementation of ALPS produces static CMOS layout using a cascode-switch style. We present measurements done on fabricated circuits. For a large class of functions, particularly semi-regular control logic, VLSI layout generated by ALPS compares favorably in speed and area to PLAS and Standard-Cell designs. Bertrand Serlet	DAC	1