Interference suppression is crucial for the proper operation of Synthetic Aperture Radar (SAR). In complex electromagnetic environments, when SAR systems are affected by Coherent Modulation and Forwarding (CMF) signals, Artificial Modulation Targets (AMT) may manifest in the imaging results. To solve this problem, this paper proposes an AMT reconstruction method for C/X-band SAR based on complex signal codec network, which aims to separate and cancel the AMT signals from the raw echoes. The method achieves precise AMT signal reconstruction and cancellation by three aspects. Firstly, a multi-scenario echo dataset with storage size of 65.3 GB is constructed by the authors through modeling and analyzing. Secondly, the network introduces a Large-interlayer Signal Reconstruction Link (LSRL) module to mitigate significant errors caused by size adjustments in traditional codec architectures, while dual-channel processing of amplitude and phase information significantly improves reconstruction accuracy. Thirdly, a Composite Signal Reconstruction Precision (CSRP) loss function, combining global loss and micro-cumulative-error loss, is designed to optimize the training process. The effectiveness of this method is verified by Hardware-In-Loop (HIL) experiments. Results demonstrate that the Structure Similarity Index Measure (SSIM) between reconstructed AMT signals and ground-truth injected signals reaches 0.81054, while the SSIM of interference-canceled scene imagery attains 0.85508. The comparison test proves that the CSRP loss function is superior to the traditional method in convergence and reconstruction effect, and the ablation test verifies the key role of LSRL module in improving performance. Furthermore, discussions on optimizer selection and the abrupt drops phenomenon in training loss curve provide theoretical insights for future research.

Monolithic inter-tier vias (MIVs) in monolithic 3-D integrated circuits (M3D ICs) enables massive vertical integration. However, MIVs are more susceptible to defects due to high integration density and complex manufacturing processes. Existing MIV test techniques can effectively detect and locate MIV faults, but diagnosable fault types are limited. We propose a novel fault diagnosis method based on signal transmission performance analysis. This method can diagnose more fault types, including resistive open, hard open, short, and leakage faults. In the proposed solution, fault diagnosis can be carried out by comprehensively monitoring voltage and delay characteristics of MIVs. The effectiveness of fault diagnosis is verified through high speed simulation program with integrated circuit emphasis (HSPICE) simulations. We also perform Monte Carlo simulations to prove that the proposed method has high robustness even in the case of process variations. Experimental results show that the proposed method has low hardware overhead while ensuring high diagnostic resolution.

Monolithic 3D integration realizes the vertical interconnection between adjacent layers by using nanoscale monolithic inter-tier vias (MIVs). However, MIVs are particularly vulnerable to defects due to high integration density and substantial scaling of the inter-layer dielectric. We propose a novel test method to detect open, short, and leakage faults in MIVs. Since the MIV defect will change its electrical characteristics, this method can test the MIV by identifying the voltage range divided according to different MIV faults. The effectiveness of fault detection is verified through HSPICE simulations. We also perform Monte Carlo simulations to prove the testability of the proposed method even in the case of process variations. Experimental results show that the proposed method has high detection precision while ensuring low hardware overhead.

Monolithic 3-D integrated circuits (M3D ICs) have a higher integration and better performance compared to 3-D ICs based on through-silicon vias. However, high integration density and substantial scaling of the interlayer dielectric (ILD) make M3D ICs extremely prone to occur process defects. In fact, defects such as voids often occur in the bonding process of M3D ICs. Therefore, ILD void detection is necessary in order to achieve high yield for M3D ICs. In this article, an ILD void detection method based on switched capacitors is proposed. Since voids affect the equivalent capacitance of logic gates above the ILD, voids can be discovered by measuring the gate-level equivalent capacitance. And the value of the capacitance can reflect severity of the void. The effectiveness and accuracy of the proposed method are verified by HSPICE simulations. For M3D ICs with the 22-nm process, the minimum capacitance variation identified by this method is 3.355 fF under process variation. And this means nanoscale voids can be detected by the proposed method.