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Hosein Yavarzadeh

dblp:352/6508 · DBLP profile ↗
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5ranked-venue papers
3as first author
5since 2021 · last 2026
0000-0003-0809-6230ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Security and privacy · 4 · 2 first-author · 4 since 2021Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
5 papers
Hardware security and side channels · 82% Systems and software security · 13% Cryptographic primitives and cryptanalysis · 5%
Computer architecture, parallel and distributed computing, and storage systems
5 papers
Processor architecture and microarchitecture · 100%

Topics — the 12 heaviest of 13, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware security and side channels
microarchitectural side channel
3.142026
TDXRay: Microarchitectural Side-Channel Analysis of Intel TDX for Real-World Workloads · SP 2026
Pathfinder: High-Resolution Control-Flow Attacks Exploiting the Conditional Branch Predictor · ASPLOS (3) 2024
Half&Half: Demystifying Intel's Directional Branch Predictors for Fast, Secure Partitioned Execution · SP 2023
Processor architecture and microarchitecture
branch prediction
2.842024
Indirector: High-Precision Branch Target Injection Attacks Exploiting the Indirect Branch Predictor · USENIX Security Symposium 2024
Pathfinder: High-Resolution Control-Flow Attacks Exploiting the Conditional Branch Predictor · ASPLOS (3) 2024
Half&Half: Demystifying Intel's Directional Branch Predictors for Fast, Secure Partitioned Execution · SP 2023
Hardware security and side channels › microarchitectural side channel
branch predictor side channel
1.322023
Half&Half: Demystifying Intel's Directional Branch Predictors for Fast, Secure Partitioned Execution · SP 2023
Half&Half: Demystifying Intel's Directional Branch Predictors for Fast, Secure Partitioned Execution · SP 2023
Systems and software security
isolation
1.322023
Half&Half: Demystifying Intel's Directional Branch Predictors for Fast, Secure Partitioned Execution · SP 2023
Half&Half: Demystifying Intel's Directional Branch Predictors for Fast, Secure Partitioned Execution · SP 2023
Processor architecture and microarchitecture › branch prediction
conditional branch predictor
1.322023
Half&Half: Demystifying Intel's Directional Branch Predictors for Fast, Secure Partitioned Execution · SP 2023
Half&Half: Demystifying Intel's Directional Branch Predictors for Fast, Secure Partitioned Execution · SP 2023
Hardware security and side channels › trusted execution environments
Intel TDX
1.012026
TDXRay: Microarchitectural Side-Channel Analysis of Intel TDX for Real-World Workloads · SP 2026
Hardware security and side channels
trusted execution environments
1.012026
TDXRay: Microarchitectural Side-Channel Analysis of Intel TDX for Real-World Workloads · SP 2026
Hardware security and side channels
microarchitectural attacks
0.812024
Indirector: High-Precision Branch Target Injection Attacks Exploiting the Indirect Branch Predictor · USENIX Security Symposium 2024
Hardware security and side channels › microarchitectural attacks
transient execution attack
0.812024
Pathfinder: High-Resolution Control-Flow Attacks Exploiting the Conditional Branch Predictor · ASPLOS (3) 2024
Cryptographic primitives and cryptanalysis › block cipher cryptanalysis
AES key recovery
0.212024
Pathfinder: High-Resolution Control-Flow Attacks Exploiting the Conditional Branch Predictor · ASPLOS (3) 2024
Hardware security and side channels
side-channel attack
0.212024
Indirector: High-Precision Branch Target Injection Attacks Exploiting the Indirect Branch Predictor · USENIX Security Symposium 2024
Cryptographic primitives and cryptanalysis
symmetric cryptography
0.212024
Pathfinder: High-Resolution Control-Flow Attacks Exploiting the Conditional Branch Predictor · ASPLOS (3) 2024

Methods — techniques the papers use, named apart from their topics

software fault isolation · 2.6compiler modification · 2.6side-channel analysis · 2.0prediction history table manipulation · 1.5path history register manipulation · 1.5control-flow reconstruction · 1.5branch target injection · 1.5
YearPublicationVenuePosition
2026 TDXRay: Microarchitectural Side-Channel Analysis of Intel TDX for Real-World Workloads
Tristan Hornetz, Hosein Yavarzadeh, Albert Cheu, Adrià Gascón, Lukas Gerlach 0001, Daniel Moghimi, Phillipp Schoppmann, Michael Schwarz 0001, Ruiyi Zhang 0001
SP2
2024 Pathfinder: High-Resolution Control-Flow Attacks Exploiting the Conditional Branch Predictor
abstract
This paper introduces novel attack primitives that enable adversaries to leak (read) and manipulate (write) the path history register (PHR) and the prediction history tables (PHTs) of the conditional branch predictor in high-performance CPUs. These primitives enable two new classes of attacks: first, it can recover the entire control flow history of a victim program by exploiting read primitives, as demonstrated by a practical secret-image recovery based on capturing the entire control flow of libjpeg routines. Second, it can launch extremely high-resolution transient attacks by exploiting write primitives. We demonstrate this with a key recovery attack against AES based on extracting intermediate values.
Hosein Yavarzadeh, Archit Agarwal, Max Christman, Christina Garman, Daniel Genkin, Andrew Kwong, Daniel Moghimi, Deian Stefan, Mohammadkazem Taram, Dean M. Tullsen
ASPLOS (3)1
2024 Indirector: High-Precision Branch Target Injection Attacks Exploiting the Indirect Branch Predictor
Hosein Yavarzadeh, Dean M. Tullsen
USENIX Security Symposium2
2023 Half&Half: Demystifying Intel's Directional Branch Predictors for Fast, Secure Partitioned Execution
abstract
This paper presents Half&Half, a novel software defense against branch-based side-channel attacks. Half&Half isolates the effects of different protection domains on the conditional branch predictors (CBPs) in modern Intel processors. This work presents the first exhaustive analysis of modern conditional branch prediction structures, and reveals for the first time an unknown opportunity to physically partition all CBP structures and completely prevent leakage between two domains using the shared predictor. Half&Half is a software-only solution to branch predictor isolation that requires no changes to the hardware or ISA, and only requires minor modifications to be supported in existing compilers. We implement Half&Half in the LLVM and WebAssembly compilers and show that it incurs an order of magnitude lower overhead compared to the current state-of-the-art branch-based side-channel defenses.
Hosein Yavarzadeh, Mohammadkazem Taram, Shravan Narayan, Deian Stefan, Dean M. Tullsen
SP1
2023 Half&Half: Demystifying Intel's Directional Branch Predictors for Fast, Secure Partitioned Execution
abstract
This paper presents Half&Half, a novel software defense against branch-based side-channel attacks. Half&Half isolates the effects of different protection domains on the conditional branch predictors (CBPs) in modern Intel processors. This work presents the first exhaustive analysis of modern conditional branch prediction structures, and reveals for the first time an unknown opportunity to physically partition all CBP structures and completely prevent leakage between two domains using the shared predictor. Half&Half is a software-only solution to branch predictor isolation that requires no changes to the hardware or ISA, and only requires minor modifications to be supported in existing compilers. We implement Half&Half in the LLVM and WebAssembly compilers and show that it incurs an order of magnitude lower overhead compared to the current state-of-the-art branch-based side-channel defenses.
Hosein Yavarzadeh, Mohammadkazem Taram, Shravan Narayan, Deian Stefan, Dean M. Tullsen
SP1