The modern supply chain ecosystem exposes hardware intellectual property (IP) blocks to diverse confidentiality attacks aimed at reverse engineering (RE), piracy, or the extraction of design secrets. An emerging and potent design solution for IP protection against these attacks, particularly against RE, is the fine-grained redaction of security-critical logic and replacing the redacted logic with lookup tables (LUTs). The LUTs are then programmed in-field, similar to FPGAs, using protected bitstreams, thereby preventing untrusted foundries or test/assembly facilities from mounting RE attacks. The LUT-based redaction paradigm incurs a substantial hardware cost, with area overhead ranging from 70x to 100x and delay overhead from 2x to 5x, while also often necessitating significant alterations to the commercial tool flow for design, verification, and testing. In this work, we propose PROM, a robust fine-grain redaction technique inspired by structured ASIC, that aims to address the limitations of LUT-based redaction with novel overhead optimizations. The redacted security-critical logic is implemented using a library of custom-design PROM cells that are optimized to minimize overheads compared to state-of-the-art redaction techniques while providing strong protection against various RE attacks. We evaluated the proposed redaction technique across a range of open-source benchmarks, achieving robust security with average overheads of 1.42x in area and 1.09x in delay, demonstrating its efficiency and practicality.

Traditional digital implementations of neural accelerators are limited by high power consumption and area overheads, while analog and non-CMOS implementations suffer from noise, device mismatch, and reliability issues. This paper introduces a CMOS Look-Up Table (LUT)-based Architecture for Neural Accelerators (LANA) that reduces the power consumption and area overhead of traditional digital implementations through precomputed, faster LUT access while avoiding noise and mismatch challenges of analog circuits. To solve the scalability issues of conventional LUT-based computation, we split high-precision multiply and accumulate (MAC) operations into lower-precision MACs using a divide-and-conquer (D&C) based approach. LANA achieves up to 29.54× lower area with 3.34× lower energy per inference task compared to traditional LUT-based techniques and up to 1.24× lower area with 1.80× lower energy per inference task than conventional digital MAC-based techniques (Wallace Tree/Array Multipliers) without retraining and without affecting the accuracy of pre-trained unpruned models, as well as on Lottery Ticket Pruned (LTP) models that already reduce the number of required MAC operations by up to 98%. Finally, we introduce mixed precision analysis in the LANA framework for all LTP pruned and unpruned models (VGG11, VGG19, Resnet18, Resnet34, GoogleNet) that achieved up to 29.59× (GoogleNet pruned)-62.83× (VGG11 unpruned) lower area across models with 3.34× (GoogleNet pruned)-8.1× (VGG11 unpruned) lower energy per inference than traditional LUT-based techniques, and up to 1.24× (GoogleNet pruned)-2.63× (VGG11 unpruned) lower area requirement with 1.81× (GoogleNet pruned)-4.37× (VGG11 unpruned) lower energy per inference across models as compared to conventional digital MAC-based techniques with 1% accuracy loss relative to the baseline.

Physical unclonable functions (PUFs) are widely used for hardware security, yet conventional designs often suffer from considerable design overhead, limited placement flexibility, and susceptibility to environmental noise. This work presents DF-PUF, a dual-function, programmable entropy source tailored for secure and resource-efficient ASIC integration. DF-PUF leverages die-level process variations to generate device-unique responses for authentication, while its hardware resources can be dynamically repurposed as memory elements for local data storage when not operating as a PUF, thereby enhancing area efficiency. The architecture supports flexible deployment across the chip layout, facilitating integration in diverse design scenarios. Additionally, DF-PUF incorporates a noise-resilient response conditioning mechanism that mitigates environmental fluctuations, ensuring that output characteristics are predominantly determined by intrinsic process variations. These capabilities are achieved with minimal overhead, making DF-PUF a practical and scalable solution for secure embedded systems. Comprehensive evaluation through circuit-level simulations and silicon measurements on 65nm CMOS test chips demonstrates the proposed design’s superior uniqueness, randomness, and robustness.

This paper presents fusion intelligence (FI), a bio-inspired paradigm that synergistically integrates the intrinsic capabilities of intelligent biological organisms with the advanced potential of artificial intelligence (AI) driven systems. FI harnesses the unique intelligence, sensing, actuation, and mobility attributes of living organisms, such as honeybees, blending these with the sophisticated data-driven problem-solving functionalities of AI. By bridging the gap between natural intelligence (NI) and AI, FI can transform how humans interact with and harness the capabilities of both natural and artificial systems. The paper presents the model of FI and its application to solve practical problems, discusses the challenges and future directions of FI research, emphasizing a generalized approach to solve complex problems, where AI can observe/control NI in a closed-loop system. We demonstrate the potential for FI to enhance the performance of an agricultural IoT system via a simulated case study, which achieves 50% improvement in the efficacy of insect pollination (entomophily).

Compute-in-memory (CiM) has emerged as a promising approach for improving energy efficiency for diverse data-intensive applications. In this paper, we present LUNA-CiM, a lookup table (LUT)-based programmable fabric for flexible and efficient mapping of artificial neural network (ANN) in memory. Its objective is to tackle scalability challenges in LUT-based computation by minimizing hardware, storage elements, and energy consumption. The proposed method utilizes the divide and conquer (D&C) strategy to enhance the scalability of LUT-based computation. For example, in a 4b × 4b lookup table-based multiplier, as one of the main components in ANN, decomposing high-precision operations into lower-precision counterparts leads to a substantial reduction in area overheads, approximately 73% less compared to conventional LUT-based approaches. Importantly, this efficiency gain is achieved without compromising accuracy. Extensive simulations were conducted to validate the performance of the proposed method. The analysis presented in this paper reveals a noteworthy advancement in energy efficiency, indicating a 58% reduction in energy consumption per computation compared to the conventional lookup table approach. Additionally, the introduced approach demonstrates a 36% improvement in speed over the traditional lookup table approach. These findings highlight notable advancements in performance, showcasing the potential of this inventive method to achieve low power, low-area overhead, and fast computations through the utilization of LUTs within an SRAM array.

This paper introduces multi-bit memory-based PUF (MBM PUF), a new PUF architecture designed to enhance the resilience of SRAM PUFs in ASIC applications. The MBM PUF utilizes an SRAM cell as its main component, capitalizing on its simplicity while mitigating weaknesses such as susceptibility to environmental noise and various attacks. As an example, a MBM PUF was implemented within an edge-triggered D flip-flop, a key component in the scan chain used by digital and mixed-signal designs, to achieve enhanced security with minimal area overhead. The concept can also be integrated into other circuits with built-in positive feedback loops, effectively leveraging their resources while minimizing die area. Simulation results in 45 nm CMOS technology show that the proposed security solution can readily fulfill the required performance criteria for a PUF.

This paper describes a programmable single-chip feedback ASIC for a network of coupled microelectromechanical systems (MEMS) referenced oscillators in the 0.4-15 MHz range. The chip contains differential low-noise amplifiers (LNAs), variable-gain amplifiers (VGAs) and programmable-gain amplifiers (PGAs) for gain control, second-order active-RC band-pass filters (BPFs) for band selection, all-pass filters (APFs) for phase shifting, an automatic level control (ALC) loop, and output buffers to drive mechanical resonators. The feedback transfer function can be fine-tuned via a three-wire serial peripheral interface (SPI) bus. A compensation path with its own PGAs, programmable attenuator, and APF enables removal of electrical feedthrough within the resonator. The chip has 5 differential input paths with independent gain control, 1–2 of which are used for local feedback (to realize oscillations) while the others accept inputs from other oscillators. The chip has been fabricated in 180 nm CMOS and consumes 4.6 mW at 1.8 V. In initial tests, it is integrated with a 2 MHz quartz resonator$(Q=2000)$to realize an oscillator with low phase noise (-117 dBc/Hz at 1 kHz offset). Additionally, the chip's ability to synchronize oscillators is validated via a 1:1 injection locking experiment.