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Marco Biasion

dblp:354/4624 · DBLP profile ↗
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2ranked-venue papers
0as first author
2since 2021 · last 2026
0009-0005-1413-1559ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › logic synthesis › logic optimization
approximate logic synthesis
1.012026
Approximate Logic Synthesis Via Iterative SMT-Based Subcircuit Rewriting · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026
Electronic design automation
logic synthesis
1.012026
Approximate Logic Synthesis Via Iterative SMT-Based Subcircuit Rewriting · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026
Electronic design automation
hardware verification and test
0.312026
Approximate Logic Synthesis Via Iterative SMT-Based Subcircuit Rewriting · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026
Electronic design automation › hardware verification and test › hardware verification
satisfiability modulo theories
0.312026
Approximate Logic Synthesis Via Iterative SMT-Based Subcircuit Rewriting · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026

Methods — techniques the papers use, named apart from their topics

satisfiability modulo theories · 1.0boolean rewriting · 1.0
YearPublicationVenuePosition
2026 Towards Input-Distribution-Aware Approximate Multiplier Generation for CNNs
abstract
Convolutional Neural Networks (CNNs) are widely used in vision-related tasks and require intensive computation, due to the large number of multiplications in their convolutional layers. Their inherent tolerance to small numerical perturbations makes them well-suited for approximate computing, which can significantly reduce circuit area and energy consumption while having a limited impact on accuracy. We present an approach for generating approximate multipliers tailored to CNN input distributions. By using multiple complementary constraints and integrating them into an SMT-based design framework, our method effectively explores the approximation design space, producing multipliers that achieve an effective accuracy–efficiency tradeoff. Compared to five state-of-the-art CNN-oriented design techniques, our approach reduces PDA (Power-Delay-Area product) by an average of 17.45% (up to 25.73%) at equivalent accuracy.
Alessandro Buccolini, Marco Biasion, Rodrigo Otoni, George A. Constantinides, Laura Pozzi 0001
DATE2
2026 Approximate Logic Synthesis Via Iterative SMT-Based Subcircuit Rewriting
abstract
This paper presents a novel iterative approach to achieve effective and efficient approximate logic synthesis (ALS). The core idea is to perform circuit rewriting in a way that is both local, i.e., is applied piece-wise to selected subcircuits, and extensive, i.e., systematically explores the design space for good solutions. Concretely, we propose SubXPAT, a new Boolean rewriting framework which iteratively employs satisfiability modulo theories (SMT) solving to select and approximate key parts of a circuit. Selection aims at finding subcircuits that at the same time include a significant number of gates and can be efficiently approximated, which is done by searching for large convex subcircuits with a limited number of inputs and outputs. Approximation is guided by the use of a parametric template, structured as a sum of products, which allows for fine-grained control over the subcircuit characteristics. SubXPAT was implemented as an open-source tool and compared against other ALS tools implementing state-of-the-art techniques. Our experimental evaluation used a broad range of arithmetic circuits with different bit-widths and our results indicate that SubXPAT generates approximate circuits that are more area-efficient than those generated by state-of-the-art techniques in 72% of the cases.
Morteza Rezaalipour, Marco Biasion, Francesco Costa, Cristian Tirelli, Lorenzo Ferretti, Rodrigo Otoni, George A. Constantinides, Laura Pozzi 0001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2