Color grading, as a crucial step in film post-production, plays an important role in emotional expression and artistic enhancement. Recently, a geometric palette-based approach to video recoloring has been introduced with impressive results. It offers an intuitive interface that allows users to alter the color of a video by manipulating a limited set of representative colors. However, this method has two primary limitations. Firstly, palette extraction is computationally expensive, often taking more than one hour to generate palettes even for medium-length videos, which significantly limits the practical application of color editing for longer videos. Secondly, the palette colors are less representative, and some primary colors may be omitted from the resulting palettes during topological simplification, making it less intuitive in color editing. To overcome these limitations, in this paper, we propose a novel approach to video recoloring. The core of our method is a set of Bézier curves that connect the dominant colors throughout the input video. By slicing these Bézier curves in RGBT space, per-frame palette can be naturally derived. During recoloring, users can select several frames of interest and modify their corresponding palettes to change the color of the video. Our method is simple and intuitive, enabling compelling time-varying recoloring results. Compared to existing methods, our approach is more efficient in palette extraction and can effectively capture the dominant colors of the video. Extensive experiments demonstrate the effectiveness of our method.

Balanced ternary digital logic circuits based on memristors and MOSFET devices are introduced. First, balanced ternary minimum gate TMIN, maximum gate TMAX and ternary inverters are designed and verified by simulation. Next, logic circuits such as ternary encoders, decoders and multiplexers are designed using these three basic gates. For further validation, a ternary 3–1 encoder was hardware-implemented successfully using in-house fabricated memristors and MOS transistors. Two different design approaches, namely the decoder-based method and the multiplexer-based method are introduced and applied to realize combinational logic circuits such as balanced ternary half-adder, multiplier, and numerical comparator. We simulate the circuits using 50nm CMOS technology parameters and BSIM models and present comparisons and analyses of the two design methods in view of the power consumption and component device counts, which can guide subsequent research and development of integrated multi-valued logic circuits. The decoder-based method has advantages both in terms of component numbers and power consumption, but the multiplexer-based method has the advantages of being based on a simple operating principle and ease of implementation.