Customers today benefit from online grocery shopping (OGS) since it makes their lives easier and more pleasant. This study examines the extension of the technology adoption model with some new variables like visibility, economic values, habit, informativeness, and website trust and their influence on the intention to use online grocery shopping by Indian customers. A structured questionnaire was developed, and 342 responses were used for analysis. Two techniques were used: firstly, structural equation modelling (PLS-SEM) was used to determine which variables had a significant influence on the intention to use OGS; in the second phase, artificial neural network modelling (ANN) was used, under a deep learning approach, to classify the relative influence of the significant predictors obtained by PLS-SEM. The study’s findings suggest that the habit has the highest impact on users’ intention to use OGS, followed by perceived usefulness, perceived ease of use and website trust. On the other side, the results of neural network analysis confirmed many SEM findings. The study will help all online grocery service providers to build their services and strategies based on the tastes and needs of their customers.

The avenue of deep learning is scarcely explored in the domain of thermal imaging. Recovering a high-resolution output from images and videos is a classical problem in many computer vision applications. In this paper, we propose an optimized pipeline for a real-time video super-resolution task using thermal camera on embedded edge device. To tackle the challenges, we make contributions in the following several aspects: 1) comparative study of selected deep learning super-resolution models; 2) constructing and optimizing an end-to-end inference pipeline; 3) using cutting edge technology to integrate the whole workflow; 4) a real-time performance was achieved using less data; 5) we have also experimented the entire pipeline on our custom thermal dataset. As a consequence, the chosen model was able to achieve a real-time speed of over 29, 36 and 45 high FPS; 32.9dB/0.889, 31.86dB/0.801 and 30.94dB/0.728 PSNR/SSIM values for 2x, 3x and 4x scaling factors respectively.

SRAM cell design is driven by the need to satisfy several stability and performance criteria for all cells in the array in an energy-efficient manner. Significant randomness of FET threshold voltages makes achieving this difficult and limits both the minimum cell size and minimum array supply voltage. Post-silicon adaptivity in the form of an adaptive-voltage scheme in a partitioned SRAM array can be used to reduce impact of variability despite lack of any spatial correlation in realizations. This paper develops a novel optimization flow for yield-aware cell sizing and voltage selection under variability given the availability of post-silicon voltage tuning. We formulate a two-stage stochastic optimization problem in which the first-stage decision is to select cell size and possible voltage levels, and the second-stage decision is to assign each partition to an optimal voltage after manufacturing. We develop closed-form statistical models of array margin behavior and yield as a function of Vdd, cell size, and array size. We solve the problem using dynamic programming that minimizes power while meeting yield constraints on read, write, and static noise margins. The proposed flow allows designs that are on average 8% and up to 17% more power-efficient than the designs in which voltages are selected uniformly. The results also indicate that at high-yield levels power savings can be up to 32% in the active mode and 71% in the standby mode.

Equation-based optimization using geometric programming (GP) for automated synthesis of analog circuits has recently gained broader adoption. A major outstanding challenge is the inaccuracy resulting from fitting the complex behavior of scaled transistors to posynomial functions. In this paper, we advance a novel optimization strategy that explicitly handles the error of the model in the course of optimization. The innovation is in enabling the successive refinement of transistor models within gradually reducing ranges of operating conditions and dimensions. Refining via a brute force requires exponential complexity. The key contribution is the development of a framework that optimizes efficient convex formulations, while using SPICE as a feasibility oracle to identify solutions that are feasible with respect to the accurate behavior rather than the fitted model. Due to the poor posynomial fit, standard GP can return grossly infeasible solutions. Our approach dramatically improves feasibility. We accomplish this by introducing robust modeling of the fitting error's sample distribution information explicitly within the optimization. To address cases of highly stringent constraints, we introduce an automated method for identifying a true feasible solution through minimal relaxation of design targets. We demonstrate the effectiveness of our algorithm on two benchmarks: a two-stage CMOS operational amplifier and a voltage-controlled oscillator designed in TSMC 0.18 μm CMOS technology. Our algorithm is able to identify superior solution points producing uniformly better power and area values under a gain constraint with improvements of up to 50% in power and 10% in area for the amplifier design. Moreover, whereas standard GP methods produced solutions with constraint violations as large as 45%, our method finds feasible solutions.

General Purpose Graphics Processing Units (GPGPUs) are rapidly becoming an integral part of high-performance system architectures. The Tianhe-1A and Tsubame systems received significant attention for their architectures that leverage GPGPUs. Increasingly many scientific applications that were originally written for CPUs using MPI for parallelism are being ported to these hybrid CPU-GPU clusters. In the traditional sense, CPUs perform computation while the MPI library takes care of communication. When computation is performed on GPGPUs, the data has to be moved from device memory to main memory before it can be used in communication. Though GPGPUs provide huge compute potential, the data movement to and from GPGPUs is both a performance and productivity bottleneck. Recently, the MVAPICH2 MPI library has been modified to directly support point-to-point MPI communication from the GPU memory [1]. Using this support, programmers do not need to explicitly move data to main memory before using MPI. This feature also enables performance improvement due to tight integration of GPU data movement and MPI internal protocols. Typically, scientific applications spend a significant portion of their execution time in collective communication. Hence, optimizing performance of collectives has a significant impact on their performance. MPI_Alltoall is a heavily used collective that has O(N2) communication, for N processes. In this paper, we outline the major design alternatives for MPI_Alltoall collective communication operation on GPGPU clusters. We propose three design alternatives and provide a corresponding performance analysis. Using our dynamic staging techniques, the latency of MPI_Alltoall on GPU clusters can be improved by 44% over a user level implementation and 31% over a send-recv based implementation for 256 KByte messages on 8 processes.

Data parallel architectures, such as General Purpose Graphics Units (GPGPUs) have seen a tremendous rise in their application for High End Computing. However, data movement in and out of GPGPUs remains the biggest hurdle to overall performance and programmer productivity. Real scientific applications utilize multi-dimensional data. Data in higher dimensions may not be contiguous in memory. In order to improve programmer productivity and to enable communication libraries to optimize non-contiguous data communication, the MPI interface provides MPI data types. Currently, state of the art MPI libraries do not provide native data type support for data that resides in GPU memory. The management of non-contiguous GPU data is a source of productivity and performance loss, because GPU application developers have to manually move the data out of and in to GPUs. In this paper, we present our design for enabling high-performance communication support between GPUs for non-contiguous data types. We describe our innovative approach to improve performance by "offloading" data type packing and unpacking on to a GPU device, and "pipelining" all data transfer stages between two GPUs. Our design is integrated into the popular MVAPICH2 MPI library for InfiniBand, iWARP and RoCE clusters. We perform a detailed evaluation of our design on a GPU cluster with the latest NVIDIA Fermi GPU adapters. The evaluation reveals that the proposed designs can achieve up to 88% latency improvement for vector data type at 4 MB size with micro benchmarks. For Stencil2D application from the SHOC benchmark suite, our design can simplify the data communication in its main loop, reducing the lines of code by 36%. Further, our method can improve the performance of Stencil2D by up to 42% for single precision data set, and 39% for double precision data set. To the best of our knowledge, this is the first such design, implementation and evaluation of non-contiguous MPI data communication for GPU clusters.

Equation-based optimization using geometric programming (GP) for automated synthesis of analog circuits has recently gained broader adoption. A major outstanding challenge is the inaccuracy resulting from fitting the complex behavior of scaled transistors to posynomial functions. Fitting over a large region can be grossly inaccurate, and in fact, poor posynomial fit can lead to failure to find a true feasible solution. On the other hand, fitting over smaller regions and then selecting the best region, incurs exponential complexity. In this paper, we advance a novel optimization strategy that circumvents these dueling problems in the following manner: by explicitly handling the error of the model in the course of optimization, we find a potentially suboptimal, but feasible solution. This solution subsequently guides a range-refinement process of our transistor models, allowing us to reduce the range of operating conditions and dimensions, and hence obtain far more accurate GP models. The key contribution is in using the available oracle (SPICE simulations) to identify solutions that are feasible with respect to the accurate behavior rather than the fitted model. The key innovation is the explicit link between the fitting error statistics and the rate of the error uncertainty set increase, which we use in a robust optimization formulation to find feasible solutions. We demonstrate the effectiveness of our algorithm on a two benchmarks: a two-stage CMOS operational amplifier and a voltage controlled oscillator designed in TSMC 0.18μm CMOS technology. Our algorithm is able to identify superior solution points producing uniformly better power and area values under gain constraint with improvements of up to 50% in power and 10% in area for the amplifier design. We also demonstrate that when utilizing the models with the same level of modeling error, our method yields solutions that meet the constraints while the violations for the standard method were as high as 45% and larger than 15% for several constraints.

SRAM cell design is driven by the need to satisfy static noise margin, write margin and read current margin (RCM) over all cells in the array in an energy-efficient manner. These constraints determine both the minimum cell size and supply voltage. RCM is set by the maximum read access time over the array. The randomness of transistor threshold voltages, and thus read times, makes maximum read time follow extreme order statistics, specifically, the Gumbel distribution which is characterized by long tails. Thus, the margin specification needs to be met at the high sigma corners in order to reach acceptable yield, resulting in oversizing and increased VDD. In this work, we demonstrate that a reduced-area bitcell design is achievable by reducing the impact of intra-array randomness through a new architecture that employs an adaptive voltage scheme in a partitioned SRAM array. The key idea is to be able to shift empirical distributions (realizations) of read time in a set of rows that form a single partition to meet the target. Because the partition is smaller than the whole array, the tail of the Gumbel distribution is significantly reduced. The adaptive voltage tuning policy is driven by the worst partition access time. For the blocks whose delay violates access time constraints, a higher voltage is selected out of the available set to gain yield, otherwise voltage is reduced for power saving. This permits smaller cell area and lower V DD at identical yield. The cost of adaptivity is in generation and routing of a small number (in our experiments, four) voltage levels and the area of one-per-partition set of PMOS switches. We demonstrate that through the voltage tuning architecture we propose, it is possible to obtain mean power consumption reduction on average by 21% iso-area. Alternatively, bitcell area can be reduced on average by 7% iso-power compared to the existing design strategy.

It is known that ramp-based models are not sufficient for accurate timing modeling. In this paper, we develop a technique that accurately models the waveforms, and also allows a flexible trade-off of accuracy vs. computational and representational cost. The technique is based on Singular Value Decomposition (SVD) and it naturally leads to a more general gate delay model which can be applied in any timing analysis engine with minor modifications. We demonstrate its application in timing analysis by propagating a waveform along a path. When compared with Spice, the proposed model shows good accuracy.

The gain-based technology mapping paradigm has been successfully employed for finding minimum delay and minimum area mappings. However, existing gain-based technology mappers fail to find circuits with minimal leakage power. In this paper, we introduce algorithms and modeling strategies that enable efficient gain-based technology mapping for minimum leakage power. The proposed algorithm is probability-aware and can rigorously take into account input state probability distribution to generate a circuit mapping with minimum leakage at a given percentile. Minimizing leakage at high percentiles is essential for minimizing peak leakage, which strongly influences the cooling limits and packaging costs.The algorithms have been tested on the ISCAS85 benchmark suite. Results indicate that the mappings produced by the new algorithm consume, on average 14% lesser leakage power at the 99% percentile with 1% delay penalty when compared with the approaches used in previous gain-based mappers [2]. Also, compared to a dominant-state mapper, our approach produces mappings with 15% lesser mean value of leakage. The new algorithm also reduces leakage at high quantiles by 12.8% on average, compared to a dominant state leakage minimizing mapper and the maximum savings can be as high as 21.49% across the benchmarks. Compared to the bin based mapper [10], the runtime of the algorithm is 15X faster.

Parametric yield loss due to variability can be effectively reduced by both design-time optimization strategies and by adjusting circuit parameters to the realizations of variable parameters. The two levels of tuning operate within a single variability budget, and because their effectiveness depends on the magnitude and the spatial structure of variability their joint co-optimization is required. In this paper we develop a formal optimization algorithm for such co-optimization and link it to the control and measurement overhead via the formal notions of measurement and control complexity.

Statistical Static Timing Analysis has received wide attention recently and emerged as a viable technique for manufacturability analysis. To be useful, however, it is important that the error introduced in SSTA be significantly smaller than the manufacturing variations being modeled. Achieving such accuracy requires careful attention to the delay models and to the algorithms applied. In this paper, we propose a new sparse-matrix based framework for accurate path-based SSTA, motivated by the observation that the number of timing paths in practice is sub-quadratic based on a study of industrial circuits and the ISCAS89 benchmarks. Our sparse-matrix based formulation has the following advantages: (a) It places no restrictions on process parameter distributions; (b) It embeds accurate polynomial-based delay model which takes into account slope propagation naturally; (c) It takes advantage of the matrix sparsity and high performance linear algebra for efficient implementation. Our experimental results are very promising.

Polynomial abstraction has been developed for data abstraction of sequential circuits, where the functionality can be expressed as polynomials. The method, based on the fundamental theorem of algebra, abstracts a possibly infinite domain of input values, into a much smaller and finite one, whose size is calculated according to the degree of the respective polynomial. The abstract model preserves the system's control and data properties, which can be verified by model checking. Experiments show that our approach does not only allow an automatic verification, but also gives considerably better results than existing methods.

The increasing variability of process parameters leads to substantial parametric yield losses due to timing and leakage power constraints. Leakage power is especially affected by variability because of its exponential dependence on the highly varying transistor channel length and threshold voltage. This paper describes the new technology mapping algorithm that performs library binding to maximize parametric yield limited both by timing and power constraints. This is the first work that rigorously treats variability in circuit leakage power and delay within logic synthesis. Experiments show that moving the concerns about variability into logic synthesis is justified. The results on industrial and public benchmarks indicate that, on avenge, the reduction in stand-by power can be up to 26% and can be as high as 50% for some benchmarks. The reduction is purely due to a more effective decision-making of the mapping algorithm, and is achieved without a timing parametric yield loss. Alternatively, the algorithm leads to the delay reduction of up to 17%, with a 10% avenge possible reduction across the benchmarks, for stringent leakage constraints at a fixed yield level. Parametric yield at a fixed leakage target can also be substantially increased. In some examples, the statistical mapper leads to a 80% yield at the leakage value for which the deterministic mapper guaranteed only a 50% yield.

Today's integrated circuits with increasing complexity cause the well known state space explosion problem in verification tools. In order to handle this problem a much simpler abstract model of the design has to be created for verification. We introduce the polynomial abstraction technique, which efficiently simplifies the verification task of sequential design blocks whose functionality can be expressed as a polynomial. Through our technique, the domains of possible values of data input signals can be reduced. This is done in such a way that the abstract model is still valid for model checking of the design functionality in terms of the system's control and data properties. We incorporate polynomial abstraction into the ForSyDe methodology, for the verification of clock domain design refinements.