Despite years of research and the introduction of advanced features in 5G systems, no commercially available 5G device has yet met the stringent latency and reliability requirements defined for ultra-reliable and low-latency communication (URLLC). This raises fundamental questions about whether and how URLLC can be practically implemented under current technological constraints. To answer this question, in this work, we explore the combination of several features defined by the 3GPP standardization, including link adaptation, retransmission schemes, and scheduling algorithms. We evaluate the performance of these techniques to investigate the extent to which the requirements of URLLC can be achieved by using the NS-3 5G LENA simulator. Our results demonstrate that the shortest latency at which a reliability level of 99.999% can be achieved is 4 milliseconds, provided that the wireless channel is of exceptionally high quality. This level of performance is enabled by combining a retransmission scheme with an effective scheduling algorithm. However, in the presence of poor channel quality, it becomes necessary to relax the reliability constraint and/or provide more resources to the transmission to maintain system feasibility.

Effective teamwork translates to fewer preventable errors and higher task performance in collaborative tasks. However, in time-critical tasks, successful teamwork becomes highly challenging to attain. In such settings, often, team members have partial observability of their surroundings, incur high cost of communication, and have trouble estimating the state and intent of their teammates. To assist a team in improving teamwork at task time, my doctoral research proposes an automated task-time team intervention system. Grounded in the notion of shared mental models, the system first detects whether the team is on the same page or not. It then generates effective interventions to improve teamwork. Additionally, by leveraging past demonstrations to learn a model of team behavior, this system minimizes the need for domain experts to specify teamwork models and rules.

Gradual transformation of the synchronous generator (SG)-dominated power systems to inverter-based resource (IBR)-dominated power systems is bringing new challenges regarding power system protection. Traditional protection algorithms were originally developed for SG-dominated power systems and become less reliable in an IBR-dominated system. New protection schemes, compatible with IBR-dominated power systems, have been an ongoing topic of research. However, such research frequently omits fault-related controls or requirements that influence IBR's fault behavior significantly. This paper provides a study of the fault behavior of grid-following (GFL) and grid-forming (GFM) inverters considering fault-related controls and using electromagnetic transient (EMT) program. For both inverter models, EMT-based generic inverter models are used in this paper. Ride-through controls from IEEE-1547-2018 standards are included as necessary. In addition, the major functions of the generic models that effect fault behavior are explained. Then, the fault current contributions of the GFL and GFM inverters were simulated considering different controls and grid parameters using both a single-inverter-to-infinite-bus system and a modified IEEE 34-node system. The simulation results indicate that the fault current contribution of an inverter or an IBR-dominated system depends on the inverter's operating mode, whether the grid support function and momentary cessation is enabled or not, and fault location.

This paper presents ExPECA, an edge computing and wireless communication research testbed designed to tackle two pressing challenges: comprehensive end-to-end experimentation and high levels of experimental reproducibility. Leveraging OpenStack-based Chameleon Infrastructure (CHI) framework for its proven flexibility and ease of operation, ExPECA is located in a unique, isolated underground facility, providing a highly controlled setting for wireless experiments. The testbed is engineered to facilitate integrated studies of both communication and computation, offering a diverse array of Software-Defined Radios (SDR) and Commercial Off-The-Shelf (COTS) wireless and wired links, as well as containerized computational environments. We exemplify the experimental possibilities of the testbed using OpenRTiST, a latency-sensitive, bandwidth-intensive application, and analyze its performance. Lastly, we highlight an array of research domains and experimental setups that stand to gain from ExPECA's features, including closed-loop applications and time-sensitive networking.

In federated learning (FL), which clients and quantization levels are selected for the deep model parameters has a significant impact on learning time as well as learning accuracy. This is not a trivial issue because it is also significantly affected by factors, such as computational power, communication capacity, and data distribution. Considering these factors, we formulate a joint optimization problem for clustering and selecting clusters with quantization levels. Due to the high complexity of the formulated problem, we propose a situation-aware cluster and quantization level selection (SITUA-CQ) algorithm. In this algorithm, the FL server first assembles clients into clusters to mitigate the impact of biased data distributions and determines the most suitable clusters and quantization levels based on their computing power and channel quality. Extensive simulation results show that SITUA-CQ can reduce the round time by up to 80.3% compared to conventional algorithms.

In federated learning (FL), if the participating mobile devices have low computing power and poor wireless channel conditions and/or they do not have sufficient data for various classes, a long convergence time is required to achieve the desired model accuracy. To address this problem, we first formulate a constrained Markov decision process (CMDP) problem that aims to minimize the average time of rounds while maintaining the numbers of trained data and trained data classes above certain numbers. To obtain the optimal scheduling policy, the formulated CMDP problem is converted into an equivalent linear programming (LP). Additionally, to overcome the problem of the curse of dimensionality in CMDP, we develop a joint client selection and bandwidth allocation algorithm (J-CSBA) that jointly selects appropriate mobile devices and allocates suitable amount of bandwidth to them at each round by considering their data information, computing power, and channel gain. Evaluation results validate that J-CSBA can reduce the convergence time by up to$49\%$compared to a conventional random scheme.

We present Bayesian Team Imitation Learner (BTIL), an imitation learning algorithm to model the behavior of teams performing sequential tasks in Markovian domains. In contrast to existing multi-agent imitation learning techniques, BTIL explicitly models and infers the time-varying mental states of team members, thereby enabling learning of decentralized team policies from demonstrations of suboptimal teamwork. Further, to allow for sample- and label-efficient policy learning from small datasets, BTIL employs a Bayesian perspective and is capable of learning from semi-supervised demonstrations. We demonstrate and benchmark the performance of BTIL on synthetic multi-agent tasks as well as a novel dataset of human-agent teamwork. Our experiments show that BTIL can successfully learn team policies from demonstrations despite the influence of team members' (time-varying and potentially misaligned) mental states on their behavior.

This paper proposes a novel scheme to detect and localize the spy cameras based on AI algorithm based raw traffic analytics, named AI-aided Hidden Camera Locator (AHCL). In AHCL, the video streaming data are filtered via the SVM (support vector machine) algorithm to quickly monitor whole raw network traffic from a router to the networks first. Then, gathered traffic data are denoised by the Denoising Autoencoder (DAE) technique to improve the data quality of classification for localization, where a camera transmits video streaming. Based on the proof-of-concept implementation, the proposed scheme can achieve 99.5% positioning accuracy of camera detection with the Ensemble Neural Networks (NNs).

In federated learning (FL), which clients are selected and which quantization levels are chosen for the deep model parameters have significant impacts on the learning time as well as the learning accuracy. In this paper, we formulate a joint optimization problem on the client and quantization level selections. As a low complexity solution to the formulated problem, we develop a performance-aware client and quantization level selection (PA-CQLS) algorithm where the FL server estimates the individual round times of clients based on their computing power and channel quality, and determines the most appropriate clients and quantization levels accordingly. Simulation results show that PA-CQLS can reduce the round time by up to 70% compared to conventional algorithms.

This research explores reliability and timing issues of push notification from Bluetooth Low Energy (BLE) beacons in outdoor districts for smartphone-based interactive applications. First, beacon signals fully cover a targeted area. The second issue is that beacon infrastructure is designed for reliable performance against environmental properties. Finally, the experience quality of notification to smartphone or mobile devices takes high level even though users have mobility such as a driver in a car, a user riding a bicycle, a walking user, etc. For finding out base lines to achieve these features in interactive system design and practical deployment of smart applications based on smartphone-beacon interaction, we evaluate real performances of beacon running at outdoor places. We compare the novel notification model, named n-1 model, which merely copes with application variables with delivering content redundancy, to the typical 1-1 alignment mean of one notification with single content. The proposed model shows average 70 % improvement against those impediments.

We proposed and tested a method to estimate sleep period time (SPT) using electrodermal activity (EDA) signals. Eight healthy subjects and six obstructive sleep apnea patients participated in the experiments. Each subject's EDA signals were measured at the middle and ring fingers of the dominant hand during polysomnography (PSG). For nine of the 17 participants, wrist actigraphy was also measured for a quantitative comparison of EDA- and actigraphy-based methods. Based on the training data, we observed that sleep onset was accompanied by a gradual reduction of amplitude of the EDA signals, whereas sleep offset was accompanied by a rapid increase in amplitude of EDA signals. We developed a method based on these EDA fluctuations during sleep-wake transitions, and applied it to a test dataset. The performance of the method was assessed by comparing its results with those from a physician's sleep stage scores. The mean absolute errors in the obtained values for sleep onset, offset, and period time between the proposed method, and the results of the PSG were 4.1, 3.0, and 6.1 min, respectively. Furthermore, there were no significant differences in the corresponding values between the methods. We compared these results with those obtained by applying actigraphic methods, and found that our algorithm outperformed these in terms of each estimated parameter of interest in SPT estimation. Long awakening periods were also detected based on sympathetic responses reflected in the EDA signals. The proposed method can be applied to a daily sleep monitoring system.

In the internet era, where people are connected to each other, web server architectures have been developed and advanced. Now, we are witnessing the advent of the complex IoT (Internet of Things) era, where not only people, but also all devices on the planet are interconnected to each other and enormous amount of interactions is required. In this paper, we propose HePA (Hexagonal Platform Architecture), a platform architecture that is extremely scalable while maintaining required performance and reflecting requirements of the complex environment. We expect the HePA to become a reference architecture in this field.

Single-instruction multiple-data (SIMD) accelerators provide an energy-efficient platform to scale the performance of mobile systems while still retaining post-programmability. The central challenge is translating the parallel resources of the SIMD hardware into real application performance. In scientific applications, automatic vectorization techniques have proven quite effective at extracting large levels of data-level parallelism (DLP). However, vectorization is often much less effective for media applications due to low trip count loops, complex control flow, and non-uniform execution behavior. As a result, SIMD lanes remain idle due to insufficient DLP. To attack this problem, this paper proposes a new vectorization pass called SIMD Defragmenter to uncover hidden DLP that lurks below the surface in the form of instruction-level parallelism (ILP). The difficulty is managing the data packing/unpacking overhead that can easily exceed the benefits gained through SIMD execution. The SIMD degragmenter overcomes this problem by identifying groups of compatible instructions (subgraphs) that can be executed in parallel across the SIMD lanes. By SIMDizing in bulk at the subgraph level, packing/unpacking overhead is minimized. On a 16-lane SIMD processor, experimental results show that SIMD defragmentation achieves a mean 1.6x speedup over traditional loop vectorization and a 31% gain over prior research approaches for converting ILP to DLP.

Near-threshold operation has emerged as a competitive approach for energy-efficient architecture design. In particular, a combination of near-threshold circuit techniques and parallel SIMD computations achieves excellent energy efficiency for easy-to-parallelize applications. However, near-threshold operations suffer from delay variations due to increased process variability. This is exacerbated in wide SIMD architectures where the number of critical paths are multiplied by the SIMD width. This paper provides a systematic in-depth study of delay variations in near-threshold operations and shows that simple techniques such as structural duplication and supply voltage/frequency margining are sufficient to mitigate the timing variation problems in wide SIMD architectures at the cost of marginal area and power overhead.

Solid state disks (SSDs) have many advantages over hard disk drives, including better reliability, performance, durability, and power efficiency. However, the characteristics of SSDs are completely different from those of hard disk drives with rotating disks. To achieve the full potential performance improvement with SSDs, operating systems or applications must understand the critical performance parameters of SSDs to fine-tune their accesses. However, the internal hardware and software organizations vary significantly among SSDs and, thus, each SSD exhibits different parameters which influence the overall performance. In this paper, we propose a methodology which can extract several essential parameters affecting the performance of SSDs, and apply the extracted parameters to SSD systems for performance improvement. The target parameters of SSDs considered in this paper are 1) the size of read/write unit, 2) the size of erase unit, 3) the size of read buffer, and 4) the size of write buffer. We modify two operating system components to optimize their operations with the SSD parameters. The experimental results show that such parameter-aware management leads to significant performance improvements for large file accesses by performing SSD-specific optimizations.

In modern wireless devices, two broad classes of compute-intensive applications are common: those with high amounts of data-level parallelism, such as signal processing used in wireless baseband applications, and those that have little data-level parallelism, such as encryption. Wide single-instruction multiple-data (SIMD) processors have become popular for providing high performance, yet power efficient data engines for applications with abundant data parallelism. However, the non-data-parallel applications are relegated to a low-performance scalar datapath on these data engines while the SIMD resources are left idle. To accelerate both types of applications, we propose the design of a more flexible SIMD datapath called SIMD-Morph. In SIMD-Morph, code with data-level parallelism can be executed across the lanes in the traditional manner, but the lanes can be morphed into a feed-forward subgraph accelerator to execute scalar applications more efficiently. The morphed SIMD lanes form an accelerator that exploits both instruction-level parallelism as well as operation chaining to improve the performance of scalar code by exploiting the available resources in the SIMD lanes. Experimental results show that the performance impact is a 2.6X improvement for purely non-SIMD applications and a 1.4X improvement for the non-SIMD-ized portions of applications with data parallelism.

Various scientific computations have become so complex, and thus computation tools play an important role. In this paper, we explore the state-of-the-art framework providing high-level matrix computation primitives with MapReduce through the case study approach, and demonstrate these primitives with different computation engines to show the performance and scalability. We believe the opportunity for using MapReduce in scientific computation is even more promising than the success to date in the parallel systems literature.

Power has become the most critical design constraint for embedded handheld devices. This paper proposes a power-efficient SIMD architecture, referred to as Diet SODA, for DSP applications. The key design idea is to apply near-threshold operation on a single instruction and multiple data (SIMD) architecture to significantly lower the power consumption. The major features of Diet SODA are very wide SIMD width, scatter/gather data prefetcher, and dual mode operation. A case study was performed on digital still camera (DSC) applications; the results show that Diet SODA achieves ∼130x better performance and ∼340x better energy efficiency than a DSP solution.

MapReduce is a programming model that supports distributed and parallel processing for large-scale data-intensive applications such as machine learning, data mining, and scientific simulation. Hadoop is an open-source implementation of the MapReduce programming model. Hadoop is used by many companies including Yahoo!, Amazon, and Facebook to perform various data mining on large-scale data sets such as user search logs and visit logs. In these cases, it is very common to share the same computing resources by multiple users due to practical considerations about cost, system utilization, and manageability. However, Hadoop assumes that all cluster nodes are dedicated to a single user, failing to guarantee high performance in the shared MapReduce computation environment. In this paper, we propose two optimization schemes, prefetching and pre-shuffling, which improve the overall performance under the shared environment while retaining compatibility with the native Hadoop. The proposed schemes are implemented in the native Hadoop-0.18.3 as a plug-in component called HPMR (High Performance MapReduce Engine). Our evaluation on the Yahoo!Grid platform with three different workloads and seven types of test sets from Yahoo! shows that HPMR reduces the execution time by up to 73%.

In the past decade, the proliferation of mobile devices has increased at a spectacular rate. There are now more than 3.3 billion active cell phones in the world-a device that we now all depend on in our daily lives. The current generation of devices employs a combination of general-purpose processors, digital signal processors, and hardwired accelerators to provide giga-operations-per-second performance on milliWatt power budgets. Such heterogeneous organizations are inefficient to build and maintain, as well as waste silicon area and power. Looking forward to the next generation of mobile computing, computation requirements will increase by one to three orders of magnitude due to higher data rates, increased complexity algorithms, and greater computation diversity but the power requirements will be just as stringent. Scaling of existing approaches will not suffice instead the inherent computational efficiency, programmability, and adaptability of the hardware must change. To overcome these challenges, this paper proposes an example architecture, referred to as AnySP, for the next generation mobile signal processing. AnySP uses a co-design approach where the next generation wireless signal processing and high-definition video algorithms are analyzed to create a domain specific programmable architecture. At the heart of AnySP is a configurable single-instruction multiple-data datapath that is capable of processing wide vectors or multiple narrow vectors simultaneously. In addition, deeper computation subgraphs can be pipelined across the single-instruction multiple-data lanes. These three operating modes provide high throughput across varying application types. Results show that AnySP is capable of sustaining 4G wireless processing and high-definition video throughput rates, and will approach the 1000 Mops/mW efficiency barrier when scaled to 45nm.

Previous studies have shown that wireless DSP algorithms exhibit high levels of data level parallelism (DLP). Commercial and research work in the field of software defined radio (SDR) has produced designs utilizing single-instruction multiple-data (SIMD) execution units to exploit this high level of parallelism. These designs have been able to deliver the efficiency and computational power needed to process 3G wireless technologies. Though efficient 3G processing has been achieved, next generation 4G SDR technology requires 10–1000x more computational performance but limits the power budget increase to 2–5x. In this paper, we present a breakdown of 4G and analyze the scalability of SIMD to see if it can help to meet the 4G requirement. We take a proposed SDR architecture, SODA, and modify it for different widths in order to calculate its efficiency. We consider the trade-offs with respect to computation and energy efficiency.

With the multitude of existing and upcoming wireless standards, it is becoming increasingly difficult for hardware-only baseband processing solutions to adapt to the rapidly changing wireless communication landscape. Software defined radio (SDR) promises to deliver a cost effective and flexible solution by implementing a wide variety of wireless protocols in software. In previous work, a fully programmable multicore architecture, SODA, was proposed that was able to meet the real-time requirements of 3G wireless protocols. SODA consists of one ARM control processor and four wide single instruction multiple data (SIMD) processing elements. Each processing element consists of a scalar and a wide 512-bit 32-lane SIMD datapath. A commercial prototype based on the SODA architecture, Ardbeg (named after a brand of Scotch whisky), has been developed. In this paper, we present the architectural evolution of going from a research design to a commercial prototype, including the goals, tradeoffs, and final design choices. Ardbegpsilas redesign process can be grouped into the following three major areas: optimizing the wide SIMD datapath, providing long instruction word (LIW) support for SIMD operations, and adding application-specific hardware accelerators. Because SODA was originally designed with 180 nm technology, the wide SIMD datapath is re-optimized in Ardbeg for 90 nm technology. This includes re-evaluating the most efficient SIMD width, designing a wider SIMD shuffle network, and implementing faster SIMD arithmetic units. Ardbeg also provides modest LIW support by allowing two SIMD operations to issue in the same cycle. This LIW execution supports SDR algorithmspsila most common parallel SIMD execution patterns with minimal hardware overhead. A viable commercial SDR solution must be competitive with existing ASIC solutions. Therefore, algorithm-specific hardware is added for performance bottleneck algorithms while still maintaining enough flexibility to support multiple wireless protocols. The combination of these architectural improvements allows Ardbeg to achieve 1.5-7x speedup over SODA across multiple wireless algorithms while consuming less power.