The Flex Power FPGA design is presented as a novel FPGA design offering the ability to configure the trade-off between power consumption and speed for each logic element by adjusting the threshold voltage. This design targets the reduction of static power consumption, which has become one of the most important issues in the development of future-generation devices. A method to effectively assign threshold voltages to transistors at a prescribed granularity based on a timing analysis of the mapped circuit is implemented using the VPR simulator, and the static power reduction for 70 nm technologies is estimated using MCNC benchmark circuits. Simulation results show that the average static power can be reduced to as little as 1/30 of that in the corresponding conventional FPGA. This design is also demonstrated to be effective with future technologies, where the proportion of static power will be greater.