A key challenge in using timing-robust asynchronous circuit styles is the lack of automated optimization techniques. In this paper, technology mapping and cell merger algorithms for asynchronous threshold networks are introduced. The cell merger problem is a restricted form of technology mapping where only adjacent cells are merged. The two algorithms can each target either delay or area, or a combined delay-area cost function. Experiments were performed on substantial industrial design examples (DES and GCD circuits) that had already been optimized by an existing commercial asynchronous synthesis tool flow. Average delay improvements of 31.6% for basic technology mapping and 29.6% for basic cell merger were obtained. Average area improvements of 9.5% for basic technology mapping and 8.5% for basic cell merger were also obtained. Additional experiments were performed on the largest MCNC combinational benchmarks with similar results. Finally, targeting a hybrid cost function, area minimization under specified hard timing constraints, a further area reduction of up to 10.7% on average in technology mapping was recovered without compromising the overall system performance. The new algorithms are the first systematic and general mapping approach for asynchronous threshold networks, targeting delay or area, which preserve the timing-robustness properties of the initial unoptimized circuits.

As process, temperature and voltage variations become significant in deep submicron design, timing closure becomes a critical challenge using synchronous CAD flows. One attractive alternative is to use robust asynchronous circuits which gracefully accommodate timing discrepancies. However, these asynchronous circuits typically suffer from high area and latency overhead. In this paper, an optimization algorithm is presented which reduces the area and delay of these circuits by relaxing their overly-restrictive style. The algorithm was implemented and experiments performed on a subset of MCNC circuits. On average, 49.2% of the gates could be implemented in a relaxed manner, 34.9% area improvement was achieved, and 16.1% delay improvement was achieved using a simple heuristic for targeting the critical path in the circuit. This is the first proposed approach that systematically optimizes asynchronous circuits based on the notion of local relaxation while still preserving the circuit's overall timing-robustness.

In designing asynchronous circuits it is critical to ensure that cir-cuits are free of hazards in the specified set of input transitions. In this paper, two new algorithms are proposed to determine if a com-binational circuit is hazard-free without exploring all its gates, thus providing more efficient hazard detection. Experimental results in-dicate that the best new algorithm on average visits only 20.7% of the original gates, with an average runtime speedup of 1.69 and best speedup of 2.27 (for the largest example.

Recently, vast amounts of research efforts have been made to derive a higher-level abstraction mechanism than the class abstraction in object oriented languages. Notable examples include the research activities on software architectures and component based software development. Of these, software architectures allow us to focus on the issue of software connectors, which are used to describe interactions between software components in the context of architectural styles. However, few contemporary programming languages support the explicit notion of connectors, which makes it difficult to practice software development based on software architectural concepts. The authors present their experience in implementing software connectors through first-class methods in the Java programming language. They view software connectors as methods over methods and show that a suitable set of reflective facilities can be a nice device for implementing software connectors.

Communication systems can be characterized by high reliability requirements, complexity in development, and distribution of processes and resources. In developing these kinds of systems, formal methods can be fruitful in achieving high quality of resulting systems. LOTOS, a formal specification language, allows us to write models of the system in an abstract but rigorous manner. In this paper, we present a "behavior compiler" that supports rapid prototyping by generating C++ code from LOTOS behavioral specifications. Execution of the generated code allows us to detect analysis and design errors at the early stage of system development life cycle.