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Kait Lam

dblp:362/9328 · DBLP profile ↗
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4ranked-venue papers
1as first author
4since 2021 · last 2025
0009-0001-2599-2259ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 4 · 1 first-author · 4 since 2021Theory of computation · 2 · 1 first-author · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Software engineering, system software, and programming languages
2 papers
Compilers and program optimization · 46% Concurrent programming · 34% Program verification · 20%
Network and information security
1 paper
Hardware security and side channels · 100%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Compilers and program optimization
compiler correctness
0.912025
Translation Validation for LLVM's AArch64 Backend · Proc. ACM Program. Lang. 2025
Program verification
mechanized verification
0.912025
Translation Validation for LLVM's AArch64 Backend · Proc. ACM Program. Lang. 2025
Compilers and program optimization › verified compilation
translation validation
0.912025
Translation Validation for LLVM's AArch64 Backend · Proc. ACM Program. Lang. 2025
Hardware security and side channels › side channel
speculative execution vulnerabilities
0.812024
Detecting Speculative Execution Vulnerabilities on Weak Memory Models · FM (1) 2024
Concurrent programming
speculative execution
0.812024
Detecting Speculative Execution Vulnerabilities on Weak Memory Models · FM (1) 2024
Concurrent programming › memory models
weak memory models
0.812024
Detecting Speculative Execution Vulnerabilities on Weak Memory Models · FM (1) 2024
Compilers and program optimization
compiler back end
0.312025
Translation Validation for LLVM's AArch64 Backend · Proc. ACM Program. Lang. 2025

Methods — techniques the papers use, named apart from their topics

information flow logic · 1.5Isabelle/HOL · 1.5formal semantics · 0.9alive2 · 0.9
YearPublicationVenuePosition
2025 Translation Validation for LLVM's AArch64 Backend
abstract
LLVM’s backends translate its intermediate representation (IR) to assembly or object code. Alongside register allocation and instruction selection, these backends contain many analogues of components traditionally associated with compiler middle ends: dataflow analyses, common subexpression elimination, loop invariant code motion, and a first-class IR—MIR, the “machine IR.” In effect, this kind of compiler backend is a highly optimizing compiler in its own right, with all of the correctness hazards entailed by a million lines of intricate C++. As a step towards gaining confidence in the correctness of work done by LLVM backends, we have created arm-tv, which formally verifies translations between LLVM IR and AArch64 (64-bit ARM) code. Ours is not the first translation validation work for LLVM, but we have advanced the state of the art along multiple fronts: arm-tv is a checking validator that enforces numerous ABI rules; we have extended Alive2 (which we reuse as a verification backend) to deal with unstructured mixes of pointers and integers that are typical of assembly code; we investigate the tradeoffs between hand-written AArch64 semantics and those derived mechanically from ARM’s published formal semantics; and, we have used arm-tv to discover 45 previously unknown miscompilation bugs in this LLVM backend, most of which are now fixed in upstream LLVM.
Ryan Berger, Mitch Briles, Nader Boushehrinejad Moradi, Nicholas Coughlin, Kait Lam, Nuno P. Lopes, Stefan Mada, Tanmay Tirpankar, John Regehr
Proc. ACM Program. Lang.5
2024 Detecting Speculative Execution Vulnerabilities on Weak Memory Models
abstract
Abstract Speculative execution attacks affect all modern processors and much work has been done to develop techniques for detection of associated vulnerabilities. Modern processors also operate on weak memory models which allow out-of-order execution of code. Despite this, there is little work on looking at the interplay between speculative execution and weak memory models. In this paper, we provide an information flow logic for detecting speculative execution vulnerabilities on weak memory models. The logic is general enough to be used with any modern processor, and designed to be extensible to allow detection of vulnerabilities to specific attacks. The logic has been proven sound with respect to an abstract model of speculative execution in Isabelle/HOL.
Nicholas Coughlin, Kait Lam, Graeme Smith 0001, Kirsten Winter
FM (1)2
2024 Lift-Offline: Instruction Lifter Generators
Nicholas Coughlin, Alistair Michael, Kait Lam
SAS3
2023 Lift-off: Trustworthy ARMv8 semantics from formal specifications
Kait Lam, Nicholas Coughlin
FMCAD1