Demo Data from SIGIR 2026 / reviewers in the wild / expert
Shaoqi Yang
dblp:365/8110
· DBLP profile ↗
3ranked-venue papers
1as first author
3since 2021 · last 2026
0009-0000-2821-579XORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-author · 2 since 2021Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Storage systems · 69% Memory systems · 28% Integrated circuit design · 3% |
Topics — the 12 heaviest of 12, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Storage systems
flash and SSD |
1.7 | 2 | 2025 | Retention Accelerated Testing for 3-D QLC nand Flash Memory: Characterization, Analysis, and Modeling · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025 High-Precision Error Bit Prediction for 3D QLC NAND Flash Memory: Observations, Analysis, and Modeling · IEEE Trans. Computers 2025 |
Storage systems › flash and SSD › flash memory
NAND flash |
1.7 | 2 | 2025 | Retention Accelerated Testing for 3-D QLC nand Flash Memory: Characterization, Analysis, and Modeling · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025 High-Precision Error Bit Prediction for 3D QLC NAND Flash Memory: Observations, Analysis, and Modeling · IEEE Trans. Computers 2025 |
Memory systems › processing-in-memory
logic-in-memory |
1.0 | 1 | 2026 | Universal content-addressable memory with high-endurance flash for functionally complete logic-in-memory computing · Sci. China Inf. Sci. 2026 |
Memory systems
processing-in-memory |
1.0 | 1 | 2026 | Universal content-addressable memory with high-endurance flash for functionally complete logic-in-memory computing · Sci. China Inf. Sci. 2026 |
Storage systems › flash and SSD › flash memory › NAND flash
3D NAND flash |
0.9 | 1 | 2025 | High-Precision Error Bit Prediction for 3D QLC NAND Flash Memory: Observations, Analysis, and Modeling · IEEE Trans. Computers 2025 |
Storage systems › storage reliability › durability
data retention |
0.9 | 1 | 2025 | Retention Accelerated Testing for 3-D QLC nand Flash Memory: Characterization, Analysis, and Modeling · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025 |
Storage systems › flash and SSD
flash memory reliability |
0.9 | 1 | 2025 | Retention Accelerated Testing for 3-D QLC nand Flash Memory: Characterization, Analysis, and Modeling · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025 |
Storage systems › flash and SSD › flash memory › flash storage
program/erase cycles |
0.9 | 1 | 2025 | High-Precision Error Bit Prediction for 3D QLC NAND Flash Memory: Observations, Analysis, and Modeling · IEEE Trans. Computers 2025 |
Memory systems › DRAM
rowhammer |
0.9 | 1 | 2025 | High-Precision Error Bit Prediction for 3D QLC NAND Flash Memory: Observations, Analysis, and Modeling · IEEE Trans. Computers 2025 |
Storage systems
storage reliability |
0.9 | 1 | 2025 | Retention Accelerated Testing for 3-D QLC nand Flash Memory: Characterization, Analysis, and Modeling · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025 |
Memory systems
content-addressable memory |
0.3 | 1 | 2026 | Universal content-addressable memory with high-endurance flash for functionally complete logic-in-memory computing · Sci. China Inf. Sci. 2026 |
Integrated circuit design
digital circuit design |
0.3 | 1 | 2026 | Universal content-addressable memory with high-endurance flash for functionally complete logic-in-memory computing · Sci. China Inf. Sci. 2026 |
Methods — techniques the papers use, named apart from their topics
functionally complete logic · 1.0flash memory · 1.0whole-block prediction · 0.9dynamic-worst-page prediction · 0.9charge-trap cell modeling · 0.9arrhenius model · 0.9accelerated testing · 0.9
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | Universal content-addressable memory with high-endurance flash for functionally complete logic-in-memory computing
Shaoqi Yang, Xiaohuan Zhao, Guangkuo Yang, Xuepeng Zhan, Jiezhi Chen |
Sci. China Inf. Sci. | 4 |
| 2025 | High-Precision Error Bit Prediction for 3D QLC NAND Flash Memory: Observations, Analysis, and ModelingabstractIn the age of artificial intelligence, large language models (LLM) require rapid development along with massive volumes of training data and parameter storage. Over the past decade, 3D NAND flash memory has emerged as the dominant non-volatile memory technology due to its high bit density and large capacity. However, because of its 3D vertical stacking technique and array designs, 3D NAND flash memory has more complicated data loss mechanisms compared to 2D NAND flash memory. As bit densities rise to Quad-level-cells (QLC), the small read margins will further complicate and make the situation more unpredictable. In this work, we propose an error-bit prediction model in this paper for 3D QLC NAND flash memory with the charge-trap (CT) cell structure based on a thorough analysis of multiple parameters that affect the error-bit distributions, including read disturb (RD) and degradation from program/erase (PE) cycles. Specifically, we develop the whole-block prediction (WBP) and the dynamic-worst-page prediction (DWPM) models. It is shown that the proposed models can be used for high-precision error-bit prediction to guarantee data reliability in commonly used NAND-based storage systems based on the characterization results of raw NAND chips. Guangkuo Yang, Meng Zhang 0014, Xuepeng Zhan, Shaoqi Yang, Xiaohuan Zhao, Pengpeng Sang, Fei Wu 0005, Jiezhi Chen |
IEEE Trans. Computers | 5 |
| 2025 | Retention Accelerated Testing for 3-D QLC nand Flash Memory: Characterization, Analysis, and ModelingabstractThree-dimensional (3D) NAND flash memory has become quite popular and is now widely used in data centers and mobile devices due to its outstanding storage density and cost-effectiveness. Larger storage capacity is made possible by 3D quad-level cell (QLC) NAND flash memory with the charge-trap (CT) structure, which stores four bits in each cell. However, data reliability is sacrificed in exchange for greater capacity. The lifespan of data retention is crucial for non-volatile storage. Thus, an important role is played by the Arrhenius model, which is widely used for lifespan prediction and high-temperature acceleration testing. Interestingly, we discover that the conventional Arrhenius model is inaccurate after analyzing the data retention properties of 3D QLC NAND flash memory. An empirical model is proposed for changing the apparent activation energy (Ea) based on the influence of different parameters, in order to accurately predict data lifespan and perform accelerated experiments. This developed model provides a temperature-and cycle-related parameter table for Ea, which is useful for high-temperature acceleration testing examinations. Simultaneously, we observe a linear connection between the 40∘C data retention time mapping and the other temperatures. We evaluate the effects of the modified Ea model and the classic Arrhenius model with the epitaxial data and conclude that the former can reduce the error by approximately 70% to a maximum. Shaoqi Yang, Meng Zhang 0014, Xuepeng Zhan, Xiaohuan Zhao, Guangkuo Yang, Fei Wu 0005, Jiezhi Chen |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |