Demo Data from SIGIR 2026 / reviewers in the wild / expert
Youngmock Cho
dblp:370/1439
· DBLP profile ↗
2ranked-venue papers
0as first author
2since 2021 · last 2024
0009-0005-4091-6907ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware accelerators and domain-specific architectures · 50% Memory systems · 50% | |
| Artificial intelligence
1 paper |
Efficient and distributed learning · 100% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware accelerators and domain-specific architectures
machine learning accelerator |
0.8 | 1 | 2024 | MoNDE: Mixture of Near-Data Experts for Large-Scale Sparse Models · DAC 2024 |
Hardware accelerators and domain-specific architectures › machine learning accelerator › DNN inference
mixture-of-experts inference |
0.8 | 1 | 2024 | MoNDE: Mixture of Near-Data Experts for Large-Scale Sparse Models · DAC 2024 |
Memory systems › processing-in-memory
near-data processing |
0.8 | 1 | 2024 | MoNDE: Mixture of Near-Data Experts for Large-Scale Sparse Models · DAC 2024 |
Memory systems
processing-in-memory |
0.8 | 1 | 2024 | MoNDE: Mixture of Near-Data Experts for Large-Scale Sparse Models · DAC 2024 |
Machine learning › Efficient and distributed learning
model offloading |
0.2 | 1 | 2024 | MoNDE: Mixture of Near-Data Experts for Large-Scale Sparse Models · DAC 2024 |
Methods — techniques the papers use, named apart from their topics
near-data computing · 1.5expert offloading · 1.5
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | MoNDE: Mixture of Near-Data Experts for Large-Scale Sparse ModelsabstractMixture-of-Experts (MoE) large language models (LLM) have memory requirements that often exceed the GPU memory capacity, requiring costly parameter movement from secondary memories to the GPU for expert computation. In this work, we present Mixture of Near-Data Experts (MoNDE), a near-data computing solution that efficiently enables MoE LLM inference. MoNDE reduces the volume of MoE parameter movement by transferring only the hot experts to the GPU, while computing the remaining cold experts inside the host memory device. By replacing the transfers of massive expert parameters with the ones of small activations, MoNDE enables far more communication-efficient MoE inference, thereby resulting in substantial speedups over the existing parameter of-floading frameworks for both encoder and decoder operations. Kwanseok Choi, Youngmock Cho, Jaehoon Cho, Jaewoong Sim |
DAC | 3 |
| 2024 | A Low-Latency FPGA Accelerator for YOLOv3-Tiny With Flexible Layerwise Mapping and DataflowabstractObject detection models have demonstrated outstanding performance in terms of accuracy. However, mapping convolutional neural network-based object-detection models to memory and computing-constrained devices is still challenging, which commonly leads to accuracy degradation and long latency. To address the problem, this work presents a design methodology to map the YOLOv3-tiny model onto a small FPGA board, in this case the Nexys A7-100T, which only has 0.5 MB on-chip SRAM and 240 DSPs. First, we design four identical MAC arrays to maximize the throughput by utilizing both DSPs and LUTs. Second, to exploit the MACs fully, we propose a dynamic data reuse scheme that handles inter-layer and intra-layer executions effectively under a small on-chip SRAM footprint. To this end, the proposed accelerator achieves an inference speed of 76.75 frames per second and throughput of 95.08 GOPs at 100MHz and consumes power of 2.203W. Specifically, it achieves a hardware utilization rate of 82.53%, thus significantly outperforming current YOLOv3-tiny accelerators. Minsik Kim 0006, Kyoungseok Oh, Youngmock Cho, Hojin Seo, Xuan Truong Nguyen |
IEEE Trans. Circuits Syst. I Regul. Pap. | 3 |