Demo Data from SIGIR 2026 / reviewers in the wild / expert
Peiran Du
dblp:371/4884
· DBLP profile ↗
2ranked-venue papers
1as first author
2since 2021 · last 2026
0009-0008-8731-3478ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-author · 2 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
GPUs and heterogeneous computing · 38% Hardware accelerators and domain-specific architectures · 38% Memory systems · 23% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
GPUs and heterogeneous computing
GPU computing |
1.0 | 1 | 2026 | Scaling Attention Beyond GPUs for LLM Inference · HPDC 2026 |
Hardware accelerators and domain-specific architectures › machine learning accelerator › DNN inference
LLM inference |
1.0 | 1 | 2026 | Scaling Attention Beyond GPUs for LLM Inference · HPDC 2026 |
Memory systems › memory offloading
KV cache offloading |
0.3 | 1 | 2026 | Scaling Attention Beyond GPUs for LLM Inference · HPDC 2026 |
Memory systems
memory hierarchy |
0.3 | 1 | 2026 | Scaling Attention Beyond GPUs for LLM Inference · HPDC 2026 |
Methods — techniques the papers use, named apart from their topics
sparse attention · 1.0log-sum-exp fusion · 1.0CPU-GPU hybrid attention · 1.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | Scaling Attention Beyond GPUs for LLM InferenceabstractScaling inference for large language models is increasingly constrained by limited GPU memory, primarily due to the expanding intermediate states (KV caches) required for long-context generation and multi-user workloads. Once the KV cache exceeds the capacity of high-bandwidth memory, it must be offloaded to host memory and reloaded on demand, a workflow severely bottlenecked by the CPU–GPU interconnect, typically PCIe. Existing approaches exploiting offload KV caches to CPU memory and selectively reload partial segments for attention computation often underutilize CPU compute resources and suffer from accuracy degradation. We present Beyond, a drop-in runtime that integrates a smart offloading scheme to selectively identify and retain salient KV entries across continuous decoding sessions, together with a hybrid CPU–GPU attention mechanism for scalable inference. Beyond executes dense attention over recent KV entries stored in GPU memory while performing parallel, per-head sparse attention on salient contextual KV entries residing in CPU memory. The outputs are fused efficiently through a log-sum-exp scheme. During the bandwidth-constrained decoding phase, oversized KV caches are processed cooperatively by the aggregated CPU and GPU memory bandwidth, with only minimal PCIe data movement. Experiments across diverse models and workloads demonstrate that Beyond improves scalability, supports longer sequences and larger batch sizes, and outperforms existing sparse attention baselines in both efficiency and accuracy—all on commodity GPU hardware. Weishu Deng, Peiran Du, Lingfeng Xiang, Chen Zhong 0002, Faraz Ahmed, Lianjie Cao, Puneet Sharma 0001, Song Jiang 0001, Hui Lu 0001, Jia Rao |
HPDC | 3 |
| 2023 | A Time Series Data Compression Co-processor Based on RISC-V Custom Instructions
Peiran Du, Zhaohui Cai |
ICA3PP (1) | 1 |