In this paper, a neural network-based approach for the co-design of transmission channels and matching networks in chiplet-based 2.5-D integrated circuits (ICs) for radio frequency (RF) applications is presented. This work proposes a dual-neural network framework that synergizes cascaded S-parameter modeling with data augmentation techniques. First, a cascaded method is developed to accurately model the 2.5-D signal transmission channel, incorporating through-silicon vias (TSVs), redistribution layers (RDLs), and matching networks, validated against commercial circuit tools. A convolutional neural network (CNN) is then trained to inversely map S-parameter requirements to optimal structural and matching network parameters. Concurrently, a denoising diffusion probabilistic model (DDPM) generates augmented S-parameter datasets to expand the design space while reducing simulation overhead. The framework enables automated compliance with critical constraints while optimizing secondary objectives such as matching network area minimization and frequency response enhancement. This work provides a robust artificial intelligence (AI)-driven methodology for high-efficiency RF interconnects in heterogeneous integration platforms.

In this work, a comprehensive analysis and optimization method of electrical and thermal characteristics in 2.5-D integrated circuits (ICs) is performed, including rapid heat distribution modeling, integrated voltage regulator (IVR) chip modeling, and power delivery network (PDN) modeling. Based on the proposed method, chiplet placement, decoupling placement, and IVR parameter settings that compromise the total PDN impedance, IVR impedance, and thermal distribution characteristics can be obtained. First, a rapid thermal analysis method for multiple heat sources is proposed by integrating the equivalent thermal resistance method and commercial tools. The thermal method significantly improves the computational efficiency and reduces the memory usage. Then, we analyze the electrical characteristics of a typical low dropout (LDO) and model the complete 2.5-D PDN, including interposers, chiplets, IVRs, through-silicon vias (TSVs), bumps, decoupling capacitors, and other components. The electrical and thermal problems in the 2.5-D system are formulated and a Metropolis rule-based algorithm is used to derive optimal solutions. Finally, the optimal placement schemes and parameter settings are iterated under different constraints. This method allows for the adjustment of target impedance, noise current, thermal limit, and other constraints based on varying practical situations. In the time-domain analysis, it can be found that the capacitance value is reduced while maintaining the power supply performance. With high accuracy in thermal and electrical modeling, this work provides an in-depth reference for the co-design of chiplet-based 2.5-D ICs.

The utilization of modular chiplets in interposer-based 2.5-D heterogeneous systems simplifies fabrication and design, however, it also introduces significant noise challenges. This paper presents a collaborative jitter-aware optimization in 2.5-D integrated circuits (ICs), incorporating power supply induced jitter (PSIJ), system impedance, target impedance, and decoupling capacitors, based on the hybrid pre-computation and pre-storage/duplicate removal-non-dominated sorting differential evolution (PCPS/DR-NSDE) algorithm. An automatic channel model algorithm and a uniform decoupling capacitor placement strategy are proposed to improve the design efficiency. Then, the system transfer impedance, simultaneous switch current, sensitivity function, and amplification factor are individually modeled, leading to the assembly and verification of the final PSIJ in the 2.5-D system. A PCPS strategy is proposed to handle high-time-consuming modules in the objective function and a DR operation is added to improve algorithm performance. The proposed PCPS/DR-NSDE is faster than traditional algorithms and has optimal hypervolume and coverage-metric (C-metric) indicators. The procedures for further obtaining desired solutions in the Pareto front are discussed. The impact of practical constraints and target impedance is also analyzed. This work provides a collaborative optimization and analysis of jitter, noise, and impedance in 2.5-D systems.