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Haozhi Han

dblp:378/9449 · DBLP profile ↗
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4ranked-venue papers
2as first author
4since 2021 · last 2025
0009-0004-3075-3385ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 2 first-author · 4 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
4 papers
High-performance computing · 53% Hardware accelerators and domain-specific architectures · 28% GPUs and heterogeneous computing · 17%
Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 100%

Topics — the 14 heaviest of 14, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
High-performance computing
stencil computation
2.632025
SparStencil: Retargeting Sparse Tensor Cores to Scientific Stencil Computations via Structured Sparsity Transformation · SC 2025
Jigsaw: Toward Conflict-free Vectorized Stencil Computation by Tessellating Swizzled Registers · PPoPP 2025
FlashFFTStencil: Bridging Fast Fourier Transforms to Memory-Efficient Stencil Computations on Tensor Core Units · PPoPP 2025
Compilers and program optimization
code generation
0.912025
Jigsaw: Toward Conflict-free Vectorized Stencil Computation by Tessellating Swizzled Registers · PPoPP 2025
Compilers and program optimization › vectorization
SIMD vectorization
0.912025
Jigsaw: Toward Conflict-free Vectorized Stencil Computation by Tessellating Swizzled Registers · PPoPP 2025
Hardware accelerators and domain-specific architectures
machine learning accelerator
0.912025
Matrix Is All You Need: Rearchitecting Quantum Chemistry to Scale on AI Accelerators · SC 2025
High-performance computing
quantum chemistry
0.912025
Matrix Is All You Need: Rearchitecting Quantum Chemistry to Scale on AI Accelerators · SC 2025
High-performance computing
scientific computing systems
0.912025
SparStencil: Retargeting Sparse Tensor Cores to Scientific Stencil Computations via Structured Sparsity Transformation · SC 2025
GPUs and heterogeneous computing › GPU computing › tensor cores
sparse tensor core
0.912025
SparStencil: Retargeting Sparse Tensor Cores to Scientific Stencil Computations via Structured Sparsity Transformation · SC 2025
Hardware accelerators and domain-specific architectures › scientific computing accelerator
stencil computation acceleration
0.912025
FlashFFTStencil: Bridging Fast Fourier Transforms to Memory-Efficient Stencil Computations on Tensor Core Units · PPoPP 2025
Hardware accelerators and domain-specific architectures
tensor accelerator
0.912025
SparStencil: Retargeting Sparse Tensor Cores to Scientific Stencil Computations via Structured Sparsity Transformation · SC 2025
GPUs and heterogeneous computing › GPU computing
tensor cores
0.912025
FlashFFTStencil: Bridging Fast Fourier Transforms to Memory-Efficient Stencil Computations on Tensor Core Units · PPoPP 2025
High-performance computing › code optimization
vectorization
0.912025
Jigsaw: Toward Conflict-free Vectorized Stencil Computation by Tessellating Swizzled Registers · PPoPP 2025
Memory systems
memory-bound computation
0.312025
FlashFFTStencil: Bridging Fast Fourier Transforms to Memory-Efficient Stencil Computations on Tensor Core Units · PPoPP 2025
High-performance computing › performance optimization
shared memory optimization
0.312025
FlashFFTStencil: Bridging Fast Fourier Transforms to Memory-Efficient Stencil Computations on Tensor Core Units · PPoPP 2025
Hardware accelerators and domain-specific architectures › sparsity exploitation
structured sparsity
0.312025
SparStencil: Retargeting Sparse Tensor Cores to Scientific Stencil Computations via Structured Sparsity Transformation · SC 2025

Methods — techniques the papers use, named apart from their topics

swizzled register tessellation · 1.7lane-based butterfly vectorization · 1.7SVD-based dimension flattening · 1.7temporal fusion · 0.9structured sparsity transformation · 0.9low-precision matrix operations · 0.9kernel fusion · 0.9FFT · 0.9
YearPublicationVenuePosition
2025 FlashFFTStencil: Bridging Fast Fourier Transforms to Memory-Efficient Stencil Computations on Tensor Core Units
abstract
While Tensor Core Units (TCUs) excel in AI tasks, their application to HPC algorithms like stencil computations faces significant challenges due to sparsity, which leads to underutilization and exacerbates memory-bound limitations. This paper introduces FlashFFTStencil1, a memory-efficient stencil computing system designed to bridge FFT to fully-dense stencil computations on TCUs. Aimed at bound shifting, FlashFFTStencil comprises three key techniques: Kernel Tailoring on HBM fuses distinct kernels to enhance parallelism while reducing memory transfer and footprint; Architecture Aligning on SMEM restructures FFT-based stencil computations into dense matrix multiplications tailored for shared memory architecture; Computation Streamlining on TCU optimizes TCU utilization and thread parallelism by minimizing pipeline stalls and maximizing register reuse. Notably, a distinctive extension is FlashFFTStencil's ability to enable theoretically unrestricted temporal fusion by FFT. Results show that FlashFFTStencil achieves effective sparsity-free bound shifting, with an average speedup of 2.57x over the state-of-the-art. FlashFFTStencil pioneers a new era in unifying computational patterns within the HPC landscape and bridges them with cutting-edge AI-driven hardware innovations like TCUs.
Haozhi Han, Kun Li 0016, Donglin Bai, Yiwei Zhang 0009, Yunquan Zhang, Ting Cao 0003, Mao Yang 0004
PPoPP1
2025 Jigsaw: Toward Conflict-free Vectorized Stencil Computation by Tessellating Swizzled Registers
abstract
Stencil computation plays a pivotal role in numerous scientific and engineering applications. Previous studies have extensively investigated vectorization techniques to enhance in-core parallelism; however, the performance bottleneck caused by data alignment conflicts (DAC) has not been effectively resolved in all dimensions. This paper proposes Jigsaw, a conflict-free vectorization method to reduce DAC across all dimensions by tessellating swizzled finest-grained lanes. Jigsaw comprises three key components: Lane-based Butterfly Vectorization, SVD-based Dimension Flattening, and Iteration-based Temporal Merging. These components effectively address DAC across spatial and temporal dimensions. Experimental results on different machines demonstrate that Jigsaw could achieve a significant improvement compared to the state-of-the-art techniques, with an average speedup of 2.31x on various stencil kernels.
Yiwei Zhang 0009, Kun Li 0016, Haozhi Han, Yunquan Zhang, Ting Cao 0003, Mao Yang 0004
PPoPP4
2025 Matrix Is All You Need: Rearchitecting Quantum Chemistry to Scale on AI Accelerators
abstract
Scientific computing remains fundamentally misaligned with the execution paradigm of modern AI accelerators, which rely on structured, low-precision matrix operations for performance and scalability. Quantum chemistry exemplifies this gap through three core scalability limits: irregular computational patterns, fragmented hardware utilization, and limited scientific reach.
Haozhi Han, Kun Li 0016, Fusong Ju, Qi Li 0039, Hong An, Yunquan Zhang, Ting Cao 0003, Mao Yang 0004
SC1
2025 SparStencil: Retargeting Sparse Tensor Cores to Scientific Stencil Computations via Structured Sparsity Transformation
abstract
Sparse Tensor Cores offer exceptional performance gains for AI workloads by exploiting structured 2:4 sparsity. However, their potential remains untapped for core scientific workloads such as stencil computations, which exhibit irregular sparsity patterns.
Qi Li 0039, Kun Li 0016, Haozhi Han, Yunquan Zhang, Junshi Chen 0003, Hong An, Ting Cao 0003, Mao Yang 0004
SC3