The European-funded HAL4SDV project aims to advance European solutions in software-defined vehicles by introducing a hardware abstraction layer positioned between executed software and execution units. HAL4SDV includes over 60 partners across 12 countries and receives funding within the Chips Joint Undertaking under Horizon Europe since April 2024 and is coordinated by TTTech Computertechnik. The proposed hardware abstraction layer includes safety-critical scheduling and platform deployment of software tasks, and is motivated by the requirement for abstracted hardware with unified interfaces in centralized automotive architectures.This work presents a correct-by-construction workflow which is developed by academic partners to schedule and deploy periodic software tasks onto diverse execution units. The workflow facilitates the execution of the same task stack on multiple unit architectures and consists of a task model and scheduling algorithm, which is followed by platform deployment for diverse hardware units, ensuring safe execution. In this multi-partner project, a bandwidth regulation unit for hardware accelerators and a RISC-V-based multicore system with tightly coupled memories are used as target platforms.A RoboRacer driving stack is chosen for evaluation, showing the viability of our workflow to schedule autonomous driving functions. To show generalization capability, synthetic task sets are additionally used to validate our deployment workflow.

Distributed computing capabilities at the network’s edge enable new use cases, e.g., smart factories, industrial internet of things, or autonomous mobility systems. While new applications evolve, managing the resources and being capable of integrating and adjusting the execution of tasks in a distributed edge infrastructure is of great importance. For this, applications need to be migrated between different nodes. These migrations must happen without interruption, allowing the system to meet service requirements while fully utilizing all available hardware resources. Therefore, applications should also be executable on all different compute nodes in a heterogeneous edge system without interfering with each other. To this end, applications should be granted only necessary permission, especially when un-trusted applications are integrated into the system. We, therefore, propose a migration method for isolated applications across heterogeneous compute nodes in service-oriented edge architectures. A service-oriented architecture is used to decouple applications, allowing for flexible scheduling. The migration method enables the fast migration of sandboxed applications based on WebAssembly by utilizing a two-stage migration approach. The concept can utilize multiple communication protocols for management and service communication. We have implemented a proof of concept based on the Zenoh1communication protocol. While the time required depends on the communication protocol and the memory size, we achieved migration delays of under 51 milliseconds for smaller applications. By providing a method for fast migration for applications across heterogeneous compute nodes, it is possible for distributed edge infrastructures to run applications independently from each other and adjust the execution node based on changes in the system’s environment. By integrating applications into our framework, they are executed isolated and with strict access control, allowing for easier reuse.

An ongoing trend in the domain of embedded computing systems is the consolidation of functionality on few, high-performance platforms. This development also impacts real-time systems, where a shift to parallel architectures enables meeting the increased throughput demands. On these multicore platforms, memory contention is a central concern regarding time-predictability. Additionally, isolation between tasks is required to limit the impact of faults during run time. We propose a scratchpad memory-based approach to predictable execution that integrates runtime-based isolation mechanisms with an LET-based task model. In order to mitigate interference between cores, each core executes from a local memory, while the data transfers between the local memories and the shared main memory are incorporated into a global, static schedule. Our task execution model is based on the Logical Execution Time (LET) paradigm, which we extend to include explicitly scheduled data transfers similar to the Predictable Execution Model (PREM). The implementation and evaluation of our approach is ongoing and will be evaluated on a custom RISe- 'v, based multicore platform. This novel approach allows for consolidating hard real-time tasks with high demands for functional safety onto a single platform.

Neural networks are increasingly used in real-time systems, such as automated driving applications. This requires high-performance hardware with predictable timing behavior. State-of-the-art real-time hardware is limited in memory and compute resources. On the other hand, modern accelerator systems lack the necessary predictability properties, mainly due to interference in the memory subsystem.We present a new hardware architecture with an accompanying compiler-based deployment toolchain to close this gap between performance and predictability. The hardware architecture consists of a multicore vector processor with predictable cores, each with local scratchpad memories. A central management core facilitates access to shared external memory through a static schedule calculated at compile-time. The presented compiler exploits the fixed data flow of neural networks and WCET estimates of subtasks running on individual cores to compute this schedule.Through this approach, the WCET estimate of the overall system can be obtained from the subtask WCET estimates, data transfer times, and access times of the shared memory in conjunction with the schedule calculated by the compiler.