This paper presents the X-MatchPRO high-speed lossless data compression algorithm and its hardware implementation, which enables data independent throughputs of 1.6 Gbit/s compression and decompression using contemporary low-cost reprogrammable field-programmable gate array technology. A full-duplex implementation is presented that allows a combined compression and decompression performance of 3.2 Gbit/s. The features of the compression algorithm and architecture that have enabled the high throughputs are described in detail. A comparison between this device and other commercially available data compressors is made in terms of technology, compression ratio, and throughput. X-MatchPRO is a fully synchronous design proven in silicon specially targeted to improve the performance of Gbit/s storage and communication applications.

This paper presents a high-performance application specific architecture for real time lossless data compression, which enables data throughputs over 1.5 Gbits/s compression and decompression using contemporary low-cost re-programmable FPGA technology. The implementation is embedded into a PCI-based system and tested at speed using a PC as the host computer.. A single FPGA is used to map all the functions in the system including the compression and decompressor cores, DMA logic, control logic and Master/Target PCI core. The independent compression and decompression channels enable a combined compression and decompression performance over 3 Gbits/s and robust self-checking hardware where each compress block can be automatically decompressed to defect hardware failures or errors introduced by the communication channel.

This paper presents the architecture of a System on Programmable Chip (SOPC) solution for embedded real-time control applications. It integrates a general-purpose processor, an application specific processor (CSP II), an AMBA compliant bus and a standard communication interface (Ethernet) on a single FPGA. The design supports high-speed, adaptive real-time control and integrates in a single device all the digital electronics, reducing the required external logic. The programming of the system is supported by software libraries that automatically transform the control law's equations into the processor's native Instruction Set.

This paper presents the design of a biologically based signal processing system implemented using standard digital inferior colliculus (IC) technology. The four-stage AM detection system is a step toward a full-pitch detection system and based on known mammalian physiology. The system is operational and has been successfully realized in field programmable grid array (FPGA) technology. Details of the system architecture, its operating principles, and the design decisions necessary to realize successfully neuromorphic systems in digital technology are given.

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This paper presents the design of a complex integrated circuit realised through a novel on-line test methodology. The circuit and its exact conventional equivalent both have been realised in FPGA technology. As such it represents one of the more complex designs realised to date using on-line test approaches. The approach used IFIS (If it Fails It Stops) incorporates dual-rail coding of individual data and a handshaking protocol, which substantially simplifies the detection of failure. Details of the IFIS methodology are given. The IFIS and conventional re-design of a commercial UART are reported, focusing on methodological issues as well as size and speed. Output traces are shown for the IFIS UART on FPGA operating under fault-free conditions and with deliberate failures injected.

Neural networks are valuable tools for the support of a wide range of image processing applications. For video-rate operation, special-purpose parallel hardware is often necessary. One of the most common architectures used for this purpose is the linear systolic array. The design and implementation of multi-layer neural networks in linear systolic arrays can be complex, however. This paper demonstrates that the smallest network is not necessarily the best in terms of learning or recall times. Furthermore, this paper shows that the manner in which networks are mapped into a particular hardware structure affects both the performance of the application and the efficiency with which the hardware resources are used. We analyze and identify how to best structure neural networks to optimize network performance for throughput, latency and the efficiency with which the hardware is used. We use the HANNIBAL neural network processor as a research vehicle for these investigations and demonstrate the value of the proposed techniques by a number of example applications.

Linear systolic processor arrays are a widely proposed digital architecture for neural networks. This paper reports the analysis of a range of training algorithms implemented on a linear systolic ring, with a view to (a) identifying low-level instruction requirements, (b) assessing different hardware structures for PE implementation and (c) evaluating the impact of different array controller designs. Quantitative data is derived and used to determine cost-effective PE and controller hardware constructs.

An analytical model is presented for assessing the performance of multilayer neural networks implemented in linear arrays. Metrics to assess latency, throughput rate, and computational and input-output bandwidth are developed. These metrics demonstrate a rich and complex interaction between the performance of the hardware and the number and relative dimensions of the layers in a network. Practical illustration of the use of these metrics is demonstrated for a two-hidden-layer network.>

The application of artificial neural networks to real-time image processing tasks requires the use of dedicated, high performance hardware. A linear array processor called HANNIBAL has been developed which implements the backpropagation neural learning algorithm on-chip. This paper considers the design of a complete neural system which integrates HANNIBAL into an existing image processing environment. The goals for the design of the system have been set partly by the primary application, namely feature recognition, but mainly by the desire for a flexible, high performance hardware tool for the study and evaluation of range of neural image processing applications.