In the design cycle of high-performance integrated circuits, it is common that certain components are designed directly at the transistor level. This level of design representation may not be appropriate for test generation tools that usually require a model expressed at the gate level. Logic extraction is a key step in test model generation to produce a gate-level netlist from the transistor-level representation. This is a semi-automated process which is error-prone. Once a test model is found to be erroneous, manual debugging is required, which is a resource-intensive and time-consuming process. This paper presents an in-depth analysis of typical sets of extraction errors found in the test model representations of the pipelines in high-performance designs today. It also develops an automated debugging solution for single extraction errors for pipelines with no state equivalence information. A suite of experiments on circuits with similar architecture to that found in the industry confirms the fitness and practicality of the solution.

Test model generation is common in the design cycle of custom made high performance low power designs targeted for high volume production. Logic extraction is a key step in test model generation to produce a logic level netlist from the transistor level representation. This is a semi-automated process which is error prone. The paper analyzes typical extraction errors applicable to clocking schemes seen in high-performance designs today. An automated debugging solution for these errors in designs with no state equivalence information is also presented. A suite of experiments on circuits with similar architectures to those found in the industry confirm the fitness and practicality of the solution.

Scan-based transition tests are added to improve the detection of speed failures in sequential circuits. Empirical data suggests that both data volume and application time will increase dramatically for such transition testing. Techniques to address the above problem for a class of transition tests, called enhanced transition tests, are proposed in this article.The first technique, which combines the proposed transition test chains with the ATE repeat capability, reduces test data volume by 46.5% when compared with transition tests computed by a commercial transition test ATPG tool. However, the test application time may sometimes increase. To address the test time issue, a new DFT technique, Exchange Scan, is proposed. Exchange scan reduces both data volume and application time by 46.5%. These techniques rely on the use of hold-scan cells and highlight the effectiveness of hold-scan design to address test time and test data volume issues. In addition, we address the problem of yield loss due to incidental overtesting of functionally-untestable transition faults, and we formulate an efficient adjustment to the algorithm to keep the overtest ratio low. Our experimental results show that up to 14.5% reduction in overtest ratio can be achieved, with an average overtest reduction of 4.68%.

Generation of ATPG patterns require a gate-level simulation model and associated constraints. If the models and the related constraints used to generate patterns are erroneous, then the patterns will likely fail on silicon. The process of debugging pattern failures on silicon using manual reason in the absence of automated techniques is very time consuming. Further, techniques used for automated defect diagnosis cannot be directly applied to this problem. In this paper we present techniques for debugging ATPG patterns failing on silicon. An automated tool that implements these techniques and is capable of debugging most common errors found in ATPG models and constraints is presented. Results from applying the capability on Intel Pentium-4 processor's ATPG patterns are presented.

Test model generation is crucial in the test generation process of a high-performance design targeted for large volume production. A key process in test model generation requires the extraction of a gate-level (logic) model from the transistor level representation of the circuit under test. Logic extraction is an error prone process due to extraction tool limitations and due to the human interference. Errors introduced by extraction require manual debugging, a resource intensive and time consuming task. This paper presents a set of extraction errors typical in an industrial environment. It also proposes an automated solution to extraction error diagnosis and correction. Experiments on circuits with similar architecture to that of high speed custom-made industrial blocks are conducted to confirm the fitness of the approach. 1

Scan based transition tests are added to improve the detection of IC speed failures using scan tests. Empirical data suggests that both data volume and application time for transition test will increase dramatically. Techniques to address this problem, for a class of transition tests called "enhanced transition tests", are proposed. The first technique, which combines the ATE repeat capability and the notion of transition test chains, reduces test data volume by 46.5%, when compared with transition tests computed by a commercial transition test ATPG tool. The test application time could increase or decrease. To address the test time issue, exchange scan, a new DFT technique, is proposed. Exchange scan reduces both data volume and application time by 46.5%. These techniques rely on the use of hold scan cells and highlight the effectiveness of hold-scan design to address test time and test data volume issues.

We present two algorithms, called list-based scheme and tree-based scheme, to compute bridging fault (BF) coverage ofIDDQtests. These algorithms use the novel ideal of “indistinguishable pairs,” which makes it more efficient and versatile than known fault simulation algorithms. Unlike known algorithms, the two algorithms can be used for combinational as well as sequential circuits and for arbitrary sets of BFs. Experiments show that the tree-based scheme is, in general, better than the list-based scheme. But the list-based scheme is better for some classes of faults.

In the absence of information about the layout, test generation and fault simulation systems must target all bridging faults. A novel algorithm, that is both time and space efficient, for simulating I/sub DDQ/ tests for all two-line bridging faults in combinational circuits is presented. Simulation results using randomly generated test sets point to the computational feasibility of targeting all two-line bridging faults. On a more theoretical note, we show that the problem of computing I/sub DDQ/ tests for all two-line bridging faults, even in some restricted classes of circuits, is intractable, and, even under some pessimistic assumptions, a complete I/sub DDQ/ test set for all two-line bridging faults also covers all multiple line, single cluster bridging faults.

Selecting a small subset of the set of functional vectors for performing I/sub DDQ/ measurement has previously been studied for leakage but not for bridging faults. Algorithms for this problem for all two line bridging faults, in combinational and sequential circuits, along with experimental results are presented.

In the absence of information about the layout and for better defect coverage test generation and fault simulation systems must target all bridging faults. The authors show that an I/sub DDQ/ Test Set that detects all two line bridging faults also detects all multiple line, single cluster bridging faults. A novel algorithm for simulating I/sub DDQ/ tests for all two-line bridging faults in combinational circuits is presented. Experimental results on using randomly generated I/sub DDQ/ test sets for detecting bridging faults are presented. These results point to the computational feasibility of targeting all two line bridging faults in combinational circuits, for the purpose of I/sub DDQ/ test generation.>