To enhance yield of fabricated chips, foundries normally insert dummy features to tape-out-ready layouts in order to improve pattern density uniformity. This process may unfortunately degrade the performance of analog/radio-frequency and high-speed digital integrated circuits. In this paper, we investigate the ways how to control pattern density distribution on different layers in analog layouts during the process of layout migration from an old technology to a new one or for design specification update in the same technology. We develop a new set of schemes for smartly modifying layout elements to improve pattern density uniformity besides the traditional dummy-insertion operation. The experimental results show that our proposed approach can account for up to 80% improvement toward the ideal density uniformity in the regular analog layouts. This promising option can significantly decrease the coupling-capacitance-induced parasitic effects due to the traditional sole dummy-insertion operation.

The conventional dummy fill insertion operation is usually conducted by foundries without taking into account circuit performance. In this paper, we propose a graph-based scheme to first modify layout interconnect geometry to improve pattern density uniformity in the analog layouts before the traditional dummy fill insertion process as an optional stage. The original analog constraints can be still preserved thanks to the mechanism of the constraint graphs used to represent the analog layouts. The experimental results show that our proposed method can improve pattern density uniformity by up to 75% for the regular analog layouts.

In this paper, we propose a new modeling method for computing coupling capacitance between interconnects on the same or different layers and substrate capacitance in the nanometer very large-scale integration circuits. The model has been developed based on a template, which is obtained on the basis of electric field approximation and followed by a curve-fitting technique to reach promising accuracy. To verify our proposed model, we develop scripts to generate thousands of layout samples which cover all possible geometric situations for CMOS 180-, 90-, and 65-nm technologies. The proposed model is compared with previously published works with reference to the extracted results from commercial tools. The experimental results show that the estimation errors of our method are much lower than 10% (2%-4% or less for most of the cases) but with significantly reduced computation effort. The proposed model is a general methodology that can be used for any nanometer technologies with different geometric parameters.

Parasitic capacitance of interconnects in the analog and mixed-signal VLSI circuits can be modeled by using physics equations or empirical curve fitting. In this paper, we propose an analytical model for computing parasitic capacitance between interconnects on different layers or on the same layer. In our method, electric flux is approximated to model different capacitive components, which combine to determine the overall equivalent capacitance. We first derive a general template for the fringe capacitance based on fundamental electromagnetic principles, followed by a fitting technique in order to reach outstanding accuracy. Based on our approach that includes no complex operators, capacitance of typical interconnect geometries can be efficiently computed. The proposed model is verified in comparison with the extracted results derived from commercial tools. The experimental results show that our proposed method can best approach the extracted results yet with significantly reduced computation time.