This paper presents a unified framework that allows high-quality dynamic Gaussian Splatting from both defocused and motion-blurred monocular videos. Due to the significant difference between the formation processes of defocus blur and motion blur, existing methods are tailored for either one of them, lacking the ability to simultaneously deal with both of them. Although the two can be jointly modeled as blur kernel-based convolution, the inherent difficulty in estimating accurate blur kernels greatly limits the progress in this direction. In this work, we go a step further towards this direction. Particularly, we propose to estimate per-pixel reliable blur kernels using a blur prediction network that exploits blur-related scene and camera information and is subject to a blur-aware sparsity constraint. Besides, we introduce a dynamic Gaussian densification strategy to mitigate the lack of Gaussians for incomplete regions, and boost the performance of novel view synthesis by incorporating unseen view information to constrain scene optimization. Extensive experiments show that our method outperforms the state-of-the-art methods in generating photorealistic novel view synthesis from defocused and motion-blurred monocular videos. Our code is available at https://github.com/hhhddddddd/dydeblur.

Currently, the security of the control logic of Programmable Logic Controllers (PLCs) is facing a serious threat, significantly impacting industrial production. Consequently, ensuring the security of PLC control logic becomes imperative. Formal verification emerges as a promising methodology for verifing PLC security through behavioral modeling and security testing. However, existing formal verification approaches primarily focus on modeling the PLC source code, overlooking the identification of compile-time errors and real-time runtime logic checks. Therefore, it is essential to apply formal verification to PLC control logic at the binary level. In this study, we introduce VoICS, a system designed to facilitate binary-level formal verification. Using reverse engineering, VoICS automatically parses PLC programs written by various programming languages at the binary level and constructs control flow graphs (CFGs). Furthermore, we use an algorithm combining two model optimization methods (i.e., trim invalid states and unnecessary states compression) to convert the reversed PLC assembly program into nuXmv format model. Lastly, VoICS establishes the corresponding constraints and performs formal verification on the model using nuXmv. The evaluation results demonstrate the capability of VoICS in identifying instances of unreliable control logic within PLC control programs, thus reinforcing the dependability of the industrial automation system.

PLC control programs are vulnerable to real-time threats, where attackers can disrupt the backhaul/front-end network of industrial production by creating numerous loops or I/O operations, leading to severe consequences. Therefore, formal verification of PLC control logic at the binary level is essential. In this study, we introduce a framework designed for formal verification of PLC control logic at the binary level. Our verification framework is based on simulation execution, which extracts the core control logic from PLC binary code. Initially, we develop an efficient framework for automating the parsing of PLC programs at the binary level and constructing their control flow graphs (CFGs). Next, we devise an algorithm to transform the reversed PLC assembly program into an smv model, a widely accepted formal verification tool. Subsequently, we generate real-time requirements relevant to industrial production and perform formal verification on the constructed models. To assess the real-time performance of our framework in safeguarding PLC systems, we implement a prototype and evaluated it across various representative ICS scenarios. The evaluation results demonstrate the capability of our proposed approach to effectively detect synchronization threats in PLC logic control programs.