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Renshuang Jiang

dblp:385/1179 · DBLP profile ↗
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4ranked-venue papers
2as first author
4since 2021 · last 2025
0009-0002-4411-8150ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 2 first-author · 3 since 2021Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware reliability and fault tolerance · 50% Embedded and real-time systems · 38% Processor architecture and microarchitecture · 12%
Network and information security
1 paper
Systems and software security · 100%
Software engineering, system software, and programming languages
1 paper
Debugging and program repair · 100%

Topics — the 8 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Systems and software security
memory safety
0.912025
Unlocking a New Rust Programming Experience: Fast and Slow Thinking with LLMs to Conquer Undefined Behaviors · DAC 2025
Systems and software security › program analysis
undefined behavior detection
0.912025
Unlocking a New Rust Programming Experience: Fast and Slow Thinking with LLMs to Conquer Undefined Behaviors · DAC 2025
Hardware reliability and fault tolerance
error detection
0.912025
FlexStep: Enabling Flexible Error Detection in Multi/Many-core Real-time Systems · DAC 2025
Embedded and real-time systems
real-time scheduling
0.912025
FlexStep: Enabling Flexible Error Detection in Multi/Many-core Real-time Systems · DAC 2025
Debugging and program repair
automated program repair
0.312025
Unlocking a New Rust Programming Experience: Fast and Slow Thinking with LLMs to Conquer Undefined Behaviors · DAC 2025
Debugging and program repair › automated program repair
LLM-based program repair
0.312025
Unlocking a New Rust Programming Experience: Fast and Slow Thinking with LLMs to Conquer Undefined Behaviors · DAC 2025
Hardware reliability and fault tolerance › redundancy
lockstep execution
0.312025
FlexStep: Enabling Flexible Error Detection in Multi/Many-core Real-time Systems · DAC 2025
Processor architecture and microarchitecture
multicore design
0.312025
FlexStep: Enabling Flexible Error Detection in Multi/Many-core Real-time Systems · DAC 2025

Methods — techniques the papers use, named apart from their topics

large language model · 1.7feedback mechanism · 1.7fast and slow thinking · 1.7
YearPublicationVenuePosition
2025 Unlocking a New Rust Programming Experience: Fast and Slow Thinking with LLMs to Conquer Undefined Behaviors
abstract
To provide flexibility and low-level interaction capabilities, the “unsafe” tag in Rust is essential, but undermines memory safety and introduces Undefined Behaviors (UBs) that reduce safety. Eliminating UBs requires a deep understanding of Rust’s safety rules and strong typing. Traditional methods require depth analysis of code, which is laborious and depends on knowledge design. The powerful semantic understanding capabilities of LLM offer new opportunities to solve this problem. Although existing large model debugging frameworks excel in semantic tasks, limited by fixed processes and lack adaptive and dynamic adjustment capabilities. Inspired by the dual process theory of decision-making (“Fast and Slow Thinking”), we present a LLM-based framework called RustBrain that automatically and flexibly minimizes UBs in Rust projects. Fast thinking extracts features to generate solutions, while slow thinking decomposes, verifies, and generalizes them abstractly. To apply verification and generalization results to solution generation, enabling dynamic adjustments and precise outputs, RustBrain integrates two thinking through a feedback mechanism. Experimental results on Miri dataset show a 94.3% pass rate and 80.4% execution rate, improving flexibility and Rust projects safety.
Renshuang Jiang, Pan Dong, Zhenling Duan, Xiaoxiang Fang, Jun Ma 0015, Shuai Zhao 0004, Zhe Jiang 0004
DAC1
2025 FlexStep: Enabling Flexible Error Detection in Multi/Many-core Real-time Systems
abstract
Reliability and real-time responsiveness in safety-critical systems have traditionally been achieved using error detection mechanisms, such as LockStep, which require pre-configured checker cores, strict synchronisation, static error detection regions, or limited preemptions. However, these core-bound hardware mechanisms often lead to significant resource over-provisioning and diminished real-time performance in modern systems where tasks with varying reliability requirements are consolidated on shared processors for efficiency and cost reduction. To address these challenges, this work presents FlexStep, a systematic solution that integrates hardware and software across the SoC, ISA, and OS scheduling layers. FlexStep features a novel microarchitecture that supports dynamic core configuration and asynchronous, preemptive error detection. The FlexStep architecture naturally allows for flexible task scheduling and error detection, enabling new scheduling algorithms that enhance both resource efficiency and real-time schedulability.
Tinglue Wang, Jiapeng Guan, Zhenghui Guo, Renshuang Jiang, Jing Li 0025, Zhe Jiang 0004
DAC6
2025 KERMIT: A BERT-Based Classification Method for Linux Kernel Crashes Through Stack Trace
Yunshan Yang, Pan Dong, Renshuang Jiang, Xiaoxiang Fang, Qirui Yu
ICIC (16)3
2025 Thetis-lathe: Guidance on Reducing Residual Safety Obstacle in System Software from Rust Source Codes
abstract
Programming languages play a crucial role in ensuring the safety of the Operating System (OS). Traditional low-level languages (e.g., C, C++), while high-performance, usually offer very limited protections on safety, and their vulnerability patches (e.g., AddressSanitizer, DangSan), while effective in mitigating some issues, are often too expensive. Rust language combines memory safety with performance, providing a fresh paradigm for constructing efficient, reliable, and dependable. However, existing Rust rely on unsafe code fragments to interface with low-level hardware and other programming languages, introducing critical issues: (1) compromised system-wide safety due to the presence of unsafe code, (2) inaccurate defect detection because of unavoidable interactions between unsafe and safe code; and (3) difficulty in finding an optimal balance between accuracy and efficiency of defect detection and elimination. In contrast to the previous work, we believe — “ prevention is always better than cure ”. Therefore, we propose a new methodology (namely Thetis) to detect and guide the minimization of unsafe fragments in Rust source code. For unsafe code detection, Thetis designs an automated inspection method based on feature extraction. For unsafe code elimination based on Unsafe Rust types and interchangeability, Thetis prop defect optimization suggestions and designs a framework to automatically provide safer code recommendations. We have designed and implemented a new tool called Thetis-lathe based on Thetis and have also ported Thetis-lathe to three mainstream Rust applications, i.e., BlogOS, rCore, and Miri Failure Set. Evaluations show that our tool improved the accuracy of defects and decreased the amount of unsafe code by 35% and undefined behavior by approximately 50%. Furthermore, Thetis-lathe speeds up the run-time about 5x compared with the sanitizer and LMbench results indicate that our approach introduces 7.6% (average) performance overhead on the entire system.
Renshuang Jiang, Pan Dong, Zhe Jiang 0004
ACM Trans. Embed. Comput. Syst.1