With the explosive growth of modern graph data, ReRAM-based graph processing paradigms are emerging as promising solutions to the “memory wall” bottleneck. However, existing paradigms often lean on overly idealized ReRAM architectures, overlooking the critical influence of various hardware faults due to the analog nature and immature fabrication processes of realistic ReRAMs. These hardware faults can lead to convergence anomalies or unacceptable output deviations (i.e., Severe Errors), undermining the reliability of ReRAM-based graph processing. While some studies enhance the reliability of ReRAM-based computation through fault-aware remapping or robust algorithm design, the unique graph execution characteristics make these efforts challenging to migrate effectively. In this work, we first develop ReGFI, a microarchitecture-level Fault Injection framework for ReRAM-based Graph processing. Unlike traditional fault injection methods that only introduce random algorithm-level faults, ReGFI precisely maps hardware faults into the microarchitectural graph execution flow to effectively characterize their effects on the execution correctness. Based on ReGFI, we propose FReRAM, a Fault-Resilient graph processing paradigm in realistic ReRAMs. Firstly, observing the fault robustness of graph vertices compared to graph edges, we reverse-map the vertex values to the non-ideal crossbar while using the edge values as inputs, for proactive SE avoidance. Then, leveraging the cell idleness in ReRAM crossbars and bit-wise reliability discrepancies of graph data, we recycle idle crossbar cells and squeeze out approximable Least Significant Bits to robust-encode the fault-sensitive bits, for further SE elimination. Experimental results exhibit that FReRAM achieves 88.84% SE reduction while incurring negligible overhead for fault-resilient ReRAM-based graph processing. Furthermore, we evaluate the effectiveness and performance of FReRAM under different hardware configurations, graph datasets, and data formats.

The burgeoning proliferation of graph data has rendered graph processing within conventional von Neumann computing architectures increasingly inefficient. Resistive Random Access Memory (ReRAM) emerges as a promising solution to circumvent the "memory wall" bottleneck encountered in graph processing. Nevertheless, the inherent non-idealities of ReRAM devices raise reliability concerns, the ramifications of which for graph processing necessitate a comprehensive exploration. In this work, we propose CraftRGP, a Comprehensive Reliability Analysis Framework Towards ReRAM-Based Graph Processing. CraftRGP simulates the operation of graph processing on ReRAM devices at the underlying hardware level, and employs software fault injection to simulate three primary fault models on ReRAM devices: permanent faults, transient faults, and sensing faults. Based on CraftRGP, we systematically evaluate the fault resilience of ReRAM-based graph processing along the dimensions of graph applications, fault models, and hardware architectures. Finally, utilizing the observed reliability characteristics with CraftRGP, we exemplify two use cases to demonstrate that CraftRGP can guide system designers to facilitate better reliability designs.